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<title><![CDATA[Special Section on VLSI Design and CAD Algorithms]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3413?rss=1</link>
<description><![CDATA[]]></description>
<dc:creator><![CDATA[Ishiura, N.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3413</dc:identifier>
<dc:title><![CDATA[Special Section on VLSI Design and CAD Algorithms]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3414</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3413</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3415?rss=1">
<title><![CDATA[Highly Efficient Comparator Design Automation for TIQ Flash A/D Converter]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3415?rss=1</link>
<description><![CDATA[<p>Threshold Inverter Quantization (TIQ) technique has been gaining its importance in high speed flash A/D converters due to its fast data conversion speed. It eliminates the need of resistor ladders for reference voltages generation which requires substantial power consumption. The key to TIQ comparators design is to generate 2<sup><I>n</I></sup> &ndash; 1 different sized TIQ comparators for an <I>n</I>-bit A/D converter. This paper presents a highly efficient TIQ comparator design methodology based on an analytical model as well as SPICE simulation experimental model. One can find any sets of TIQ comparators efficiently using the proposed method. A 6-bit TIQ A/D converter has been designed in a 0.18 &micro;m standard CMOS technology using the proposed method, and compared to the previous measured results in order to verify the proposed methodology.</p>]]></description>
<dc:creator><![CDATA[KIM, I., YOO, J., KIM, J., CHOI, K.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3415</dc:identifier>
<dc:title><![CDATA[Highly Efficient Comparator Design Automation for TIQ Flash A/D Converter]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3422</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3415</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers -- Physical Level Design</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3423?rss=1">
<title><![CDATA[A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3423?rss=1</link>
<description><![CDATA[<p>With the advent of the deep submicron age, circuit performance is strongly impacted by process variations and the influence on the circuit delay to the power-supply voltage increases more and more due to CMOS feature size shrinkage. Power grid optimization which considers the timing error risk caused by the variations and IR drop becomes very important for stable and hi-speed operation of system-on-chip. Conventionally, a lot of power grid optimization algorithms have been proposed, and most of them use IR drop as their object functions. However, the IR drop is an indirect metric and we suspect that it is vague metric for the real goal of LSI design. In this paper, first, we propose an approach which uses the "timing error risk caused by IR drop" as a direct objective function. Second, the critical path map is introduced to express the existence of critical paths distributed in the entire chip. The timing error risk is decreased by using the critical path map and the new objective function. Some experimental results show the effectiveness.</p>]]></description>
<dc:creator><![CDATA[KAWAKAMI, Y., TERAO, M., FUKUI, M., TSUKIYAMA, S.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3423</dc:identifier>
<dc:title><![CDATA[A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3430</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3423</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers -- Physical Level Design</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3431?rss=1">
<title><![CDATA[Efficient Hybrid Grid Synthesis Method Based on Genetic Algorithm for Power/Ground Network Optimization with Dynamic Signal Consideration]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3431?rss=1</link>
<description><![CDATA[<p>This paper proposes an efficient design algorithm for power/ground (P/G) network synthesis with dynamic signal consideration, which is mainly caused by <I>Ldi/dt</I> noise and <I>Cdv/dt</I> decoupling capacitance (DECAP) current in the distribution network. To deal with the nonlinear global optimization under synthesis constraints directly, the genetic algorithm (GA) is introduced. The proposed GA-based synthesis method can avoid the linear transformation loss and the restraint condition complexity in current SLP, SQP, ICG, and random-walk methods. In the proposed Hybrid Grid Synthesis algorithm, the dynamic signal is simulated in the gene disturbance process, and Trapezoidal Modified Euler (TME) method is introduced to realize the precise dynamic time step process. We also use a hybrid-SLP method to reduce the genetic execute time and increase the network synthesis efficiency. Experimental results on given power distribution network show the reduction on layout area and execution time compared with current P/G network synthesis methods.</p>]]></description>
<dc:creator><![CDATA[YANG, Y., KIMURA, S.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3431</dc:identifier>
<dc:title><![CDATA[Efficient Hybrid Grid Synthesis Method Based on Genetic Algorithm for Power/Ground Network Optimization with Dynamic Signal Consideration]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3442</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3431</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers -- Physical Level Design</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3443?rss=1">
<title><![CDATA[Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3443?rss=1</link>
<description><![CDATA[<p>It's a trend to consider the power supply integrity at early stage to improve the design quality. Specifically, floorplanning process is modified to improve the power supply as well. In the modified floorplanning process, both the floorplan and power/ground (P/G) network are adjusted to search for optimal floorplan as well as the most robust power supply. In this paper, we propose a novel algorithm to carry out this modified floorplanning. A new analytical method is proposed to estimate the voltage drop while the floorplan is varying constantly. This fast analytical voltage drop estimating method is plugged into the modified floorplanner to speed up the whole floorplanning process. Compared with previous methods, our algorithm can search for the optimal floorplan with consideration of power supply integrity more efficiently and therefore leads to better results. Furthermore, this paper also proposes a novel heuristic method to optimize the topology of P/G network. This optimization algorithm could construct a more robust power supply system. Experimental results show the method can speedup the IR-drop aware floorplanning process by about 10 times and reduce the routing area of P/G network while maintaining the floorplan quality and power supply integrity.</p>]]></description>
<dc:creator><![CDATA[WANG, X., SHI, J., CAI, Y., HONG, X.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3443</dc:identifier>
<dc:title><![CDATA[Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3450</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3443</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers -- Physical Level Design</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3451?rss=1">
<title><![CDATA[Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3451?rss=1</link>
<description><![CDATA[<p>Character projection (CP) lithography is utilized for maskless lithography and is a potential for the future photomask manufacture because it can project ICs much faster than point beam projection or variable-shaped beam (VSB) projection. In this paper, we first present a projection mask set development methodology for multi-column-cell (MCC) systems, in which column-cells can project patterns in parallel with the CP and VSB lithographies. Next, we present an INLP (integer nonlinear programming) model as well as an ILP (integer linear programming) model for optimizing a CP mask set of an MCC projection system so that projection time is reduced. The experimental results show that our optimization has achieved 33.4% less projection time in the best case than a naive CP mask development approach. The experimental results indicate that our CP mask set optimization method has virtually increased cell pattern objects on CP masks and has decreased VSB projection so that it has achieved higher projection throughput than just parallelizing two column-cells with conventional CP masks.</p>]]></description>
<dc:creator><![CDATA[SUGIHARA, M., MATSUNAGA, Y., MURAKAMI, K.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3451</dc:identifier>
<dc:title><![CDATA[Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3460</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3451</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers -- Physical Level Design</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3461?rss=1">
<title><![CDATA[Impact of Well Edge Proximity Effect on Timing]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3461?rss=1</link>
<description><![CDATA[<p>This paper studies impact of well edge proximity effect on circuit delay, based on model parameters extracted from test structures in an industrial 65 nm wafer process. Experimental results show that up to 10% of delay increase arises by the well edge proximity effect in the 65 nm technology, and it depends on interconnect length. Furthermore, due to asymmetric increase in pMOS and nMOS threshold voltages, delay may decrease in spite of the threshold voltage increase. From these results, we conclude that considering WPE is indispensable to cell characterization in the 65 nm technology.</p>]]></description>
<dc:creator><![CDATA[KANAMOTO, T., OGASAHARA, Y., NATSUME, K., YAMAGUCHI, K., AMISHIRO, H., WATANABE, T., HASHIMOTO, M.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3461</dc:identifier>
<dc:title><![CDATA[Impact of Well Edge Proximity Effect on Timing]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3464</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3461</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Letter -- Device and Circuit Modeling and Analysis</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3465?rss=1">
<title><![CDATA[Adaptive Stochastic Collocation Method for Parameterized Statistical Timing Analysis with Quadratic Delay Model]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3465?rss=1</link>
<description><![CDATA[<p>In this paper, we propose an Adaptive Stochastic Collocation Method for block-based Statistical Static Timing Analysis (SSTA). A novel adaptive method is proposed to perform SSTA with delays of gates and interconnects modeled by quadratic polynomials based on Homogeneous Chaos expansion. In order to approximate the key atomic operator MAX in the full random space during timing analysis, the proposed method adaptively chooses the optimal algorithm from a set of stochastic collocation methods by considering different input conditions. Compared with the existing stochastic collocation methods, including the one using dimension reduction technique and the one using Sparse Grid technique, the proposed method has 10x improvements in the accuracy while using the same order of computation time. The proposed algorithm also shows great improvement in accuracy compared with a moment matching method. Compared with the 10,000 Monte Carlo simulations on ISCAS85 benchmark circuits, the results of the proposed method show less than 1% error in the mean and variance, and nearly 100x speeds up.</p>]]></description>
<dc:creator><![CDATA[WANG, Y., ZENG, X., TAO, J., ZHU, H., CAI, W.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3465</dc:identifier>
<dc:title><![CDATA[Adaptive Stochastic Collocation Method for Parameterized Statistical Timing Analysis with Quadratic Delay Model]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3473</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3465</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3474?rss=1">
<title><![CDATA[Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3474?rss=1</link>
<description><![CDATA[<p>This paper proposes a closed-form eye-diagram model for on-chip distortionless transmission lines with intentionally inserted shunt conductance. We derive expressions of eye-opening both in voltage and time, by assuming a piece-wise linear waveform model. The model is experimentally verified with various length, shunt conductance and resistive termination. We also apply the proposed model to design space exploration, and demonstrate that the proposed model helps estimate the optimal shunt conductance and resistive termination according to required signaling length and throughput.</p>]]></description>
<dc:creator><![CDATA[HASHIMOTO, M., SIRIPORN, J., TSUCHIYA, A., ZHU, H., CHENG, C.-K.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3474</dc:identifier>
<dc:title><![CDATA[Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3480</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3474</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3481?rss=1">
<title><![CDATA[Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3481?rss=1</link>
<description><![CDATA[<p>Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on mesh-style clock distribution which is believed to be effective for reducing clock skew, and we evaluate clock skew considering manufacturing and design variabilities. Considering MOS transistor variation &mdash; random and spatially-correlated variation &mdash; and non-uniform flip-flop (FF) placement, we demonstrate that spatially-correlated variation and severe non-uniform FF distribution can be major sources of clock skew. We also examine the dependency of clock skew on design parameters, and reveal that finer clock mesh does not necessarily reduce clock skew.</p>]]></description>
<dc:creator><![CDATA[ABE, S., HASHIMOTO, M., ONOYE, T.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3481</dc:identifier>
<dc:title><![CDATA[Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3487</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3481</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3488?rss=1">
<title><![CDATA[New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3488?rss=1</link>
<description><![CDATA[<p>As the semiconductor feature size decreases, the crosstalk due to the capacitive coupling of interconnects influences signal propagation delay more seriously. Moreover, the increase of the operating frequency further emphasizes the necessity of more accurate timing analysis. In this paper, we propose new gate models to calculate gate output waveforms under crosstalk effects, which can be used for gate-level delay estimation. We classify the operation modes of metal-oxide-semiconductor (MOS) devices of a gate into 3 regions, and then develop simple linear models for each region. In addition, we present a non-iterative gate modeling method that is more efficient than previous iterative methods. In the experiments, the proposed method exhibits a maximum error of 10.70% and an average error of 2.63% when it computes the 50% delays of two or three complementary MOS (CMOS) inverters driving parallel wires. In comparison, the existing method has a maximum error of 25.94% and an average error of 3.62% under these conditions.</p>]]></description>
<dc:creator><![CDATA[BAE, T. I., KIM, J. W., KIM, Y. H.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3488</dc:identifier>
<dc:title><![CDATA[New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3496</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3488</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3497?rss=1">
<title><![CDATA[Timing Criticality for Timing Yield Optimization]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3497?rss=1</link>
<description><![CDATA[<p>Block-based SSTA analyzes the timing variation of a chip caused by process variations effectively. However, block-based SSTA cannot identify critical nodes, nodes that highly influence the timing yield of a chip, used as the effective guidance of timing yield optimization. In this paper, we propose a new timing criticality to identify those nodes, referred to as the timing yield criticality (TYC). The proposed TYC is defined as the change in the timing yield, which is induced by the change in the mean arrival time at a node. For efficiency, we estimate the TYC through linear approximation instead of propagating the changed arrival time at a node to its fanouts. In experiments using the ISCAS 85 benchmark circuits, the proposed method estimated TYCs with the expense of 9.8% of the runtime for the exact computation. The proposed method identified the node that gives the greatest effect on the timing yield in all benchmark circuits, except C6288, while existing methods did not identify that for any circuit. In addition, the proposed method identified 98.4% of the critical nodes in the top 1% in the effect on the timing yield, while existing methods identified only about 10%.</p>]]></description>
<dc:creator><![CDATA[PARK, H. S., KIM, W., HYUN, D. J., KIM, Y. H.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3497</dc:identifier>
<dc:title><![CDATA[Timing Criticality for Timing Yield Optimization]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3505</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3497</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3506?rss=1">
<title><![CDATA[Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3506?rss=1</link>
<description><![CDATA[<p>Physical defects that are not covered by stuck-at fault or bridging fault model are increasing in LSI circuits designed and manufactured in modern Deep Sub-Micron (DSM) technologies. Therefore, it is necessary to target non-stuck-at and non-bridging faults. A stuck-open is one such fault model that captures transistor level defects. This paper presents two methods for maximizing stuck-open fault coverage using stuck-at test vectors. In this paper we assume that a test set to detect stuck-at faults is given and we consider two formulations for maximizing stuck-open coverage using the given test set as follows. The first problem is to form a test sequence by using each test vector multiple times, if needed, as long as the stuck-open coverage is increased. In this case the target is to make the resultant test sequence as short as possible under the constraint that the maximum stuck-open coverage is achieved using the given test set. The second problem is to form a test sequence by using each test vector exactly once only. Thus in this case the length of the test sequence is maintained as the number of given test vectors. In both formulations the stuck-at fault coverage does not change. The effectiveness of the proposed methods is established by experimental results for benchmark circuits.</p>]]></description>
<dc:creator><![CDATA[HIGAMI, Y., SALUJA, K. K., TAKAHASHI, H., KOBAYASHI, S.-y., TAKAMATSU, Y.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3506</dc:identifier>
<dc:title><![CDATA[Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3513</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3506</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers -- Logic Synthesis, Test and Verification</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3514?rss=1">
<title><![CDATA[A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3514?rss=1</link>
<description><![CDATA[<p>This paper presents a unified test compression technique for scan stimulus and unknown masking data with seamless integration of test generation, test compression and all unknown response masking for high quality manufacturing test cost reduction. Unlike prior test compression methods, the proposed approach considers the unknown responses during test pattern generation procedure, and then selectively encodes the less specified bits (either 1s or 0s) in each scan slice for compression while at the same time masks the unknown responses before sending them to the response compactor. The proposed test scheme could dramatically reduce test data volume as well as the number of required test channels by using only <I>c</I> tester channels to drive <I>N</I> internal scan chains, where <I>c</I> = log<SUB>2</SUB> <I>N</I> + 2. In addition, because all the unknown responses could be exactly masked before entering into the response compactor, test loss due to unknown responses would be eliminated. Experimental results on both benchmark circuits and larger designs indicated the effectiveness of the proposed technique.</p>]]></description>
<dc:creator><![CDATA[SHI, Y., TOGAWA, N., YANAGISAWA, M., OHTSUKI, T.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3514</dc:identifier>
<dc:title><![CDATA[A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3523</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3514</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers -- Logic Synthesis, Test and Verification</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3524?rss=1">
<title><![CDATA[A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3524?rss=1</link>
<description><![CDATA[<p>This paper proposes a new parallel method of producing the adjacent net pair list from the LSI layouts, which is run on workstations connected with the network. The pair list contains pairs of adjacent nets and the probability of a bridging fault between them, and is used in fault diagnosis of LSIs. The proposed method partitions into regions each mask layer of the LSI layout, produces a pair list corresponding to each region in parallel and merges them into the entire pair list. It yields the accurate results, because it considers the faults between two wires containing different adjacent regions. The experimental results show that the proposed method has greatly reduced the processing time from more than 60 hrs. to 3 hrs.  in case of 42M-gate LSIs.</p>]]></description>
<dc:creator><![CDATA[SUEMITSU, K., ITO, T., KANAMOTO, T., TERAI, M., KOTANI, S., SAWADA, S.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3524</dc:identifier>
<dc:title><![CDATA[A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3530</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3524</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers -- Logic Synthesis, Test and Verification</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3531?rss=1">
<title><![CDATA[Fine-Grained Power Gating Based on the Controlling Value of Logic Elements]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3531?rss=1</link>
<description><![CDATA[<p>Leakage power consumption of logic elements has become a serious problem, especially in the sub-100-nanometer process. In this paper, a novel power gating approach by using the controlling value of logic elements is proposed. In the proposed method, sleep signals of the power-gated blocks are extracted completely from the original circuits without any extra logic element. A basic algorithm and a probability-based heuristic algorithm have been developed to implement the basic idea. The steady maximum delay constraint has also been introduced to handle the delay issues. Experiments on the ISCAS'85 benchmarks show that averagely 15&ndash;36% of logic elements could be power gated at a time for random input patterns, and 3&ndash;31% of elements could be stopped under the steady maximum delay constraints. We also show a power optimization method for AND/OR tree circuits, in which more than 80% of gates can be power-gated.</p>]]></description>
<dc:creator><![CDATA[CHEN, L., HORIYAMA, T., NAKAMURA, Y., KIMURA, S.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3531</dc:identifier>
<dc:title><![CDATA[Fine-Grained Power Gating Based on the Controlling Value of Logic Elements]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3538</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3531</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers -- Logic Synthesis, Test and Verification</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3539?rss=1">
<title><![CDATA[Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3539?rss=1</link>
<description><![CDATA[<p>In multi-FPGA prototyping systems for circuit verification, serialized time-multiplexed I/O technique is used because of the limited number of I/O pins of an FPGA. The verification time depends on a selection of inter-FPGA signals to be time-multiplexed. In this paper, we propose a method that minimizes the verification time of multi-FPGA systems by finding an optimal selection of inter-FPGA signals to be time-multiplexed. In the experiments, it is shown that the estimated verification time is improved 38.2% on average compared with conventional methods.</p>]]></description>
<dc:creator><![CDATA[INAGI, M., TAKASHIMA, Y., NAKAMURA, Y., TAKAHASHI, A.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3539</dc:identifier>
<dc:title><![CDATA[Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3547</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3539</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers -- Logic Synthesis, Test and Verification</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3548?rss=1">
<title><![CDATA[Advanced Assertion-Based Design for Mixed-Signal Verification]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3548?rss=1</link>
<description><![CDATA[<p>Functional and formal verification are important methodologies for complex mixed-signal design validation. However the industry is still verifying such systems by pure simulation. This process lacks on error localization and formal verifications methods. This is the existing verification gap between the analog and digital blocks within a mixed-signal system. Our approach improves the verification process by creating temporal properties named mixed-signal assertions which are described by a combination of digital assertions and analog properties. The proposed method is a new assertion-based verification flow for designing mixed-signal circuits. The effectiveness of the approach is demonstrated on a /-converter.</p>]]></description>
<dc:creator><![CDATA[JESSER, A., LAEMMERMANN, S., PACHOLIK, A., WEISS, R., RUF, J., HEDRICH, L., FENGLER, W., KROPF, T., ROSENSTIEL, W.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3548</dc:identifier>
<dc:title><![CDATA[Advanced Assertion-Based Design for Mixed-Signal Verification]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3555</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3548</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers -- Logic Synthesis, Test and Verification</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3556?rss=1">
<title><![CDATA[High-Level Synthesis of Software Function Calls]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3556?rss=1</link>
<description><![CDATA[<p>This letter presents a novel framework in high-level synthesis where hardware modules synthesized from functions in a given ANSI-C program can call the other <I>software</I> functions in the program. This enables high-level synthesis from C programs that contains calls to hard-to-synthesize functions, such as dynamic memory management, I/O request, or very large and complex functions. A single-thread implementation scheme is shown, whose correctness has been verified through register transfer level simulation.</p>]]></description>
<dc:creator><![CDATA[NISHIMURA, M., ISHIURA, N., ISHIMORI, Y., KANBARA, H., TOMIYAMA, H.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3556</dc:identifier>
<dc:title><![CDATA[High-Level Synthesis of Software Function Calls]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3558</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3556</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Letters -- High-Level Synthesis and System-Level Design</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3559?rss=1">
<title><![CDATA[Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3559?rss=1</link>
<description><![CDATA[<p>In real-time data-dominated communication and multimedia processing applications, a multi-layer memory hierarchy is typically used to enhance the system performance and also to reduce the energy consumption. Savings of dynamic energy can be obtained by accessing frequently used data from smaller on-chip memories rather than from large background memories. This paper focuses on the reduction of the dynamic energy consumption in the memory subsystem of multidimensional signal processing systems, starting from the high-level algorithmic specification of the application. The paper presents a formal model which identifies those parts of arrays more intensely accessed, taking also into account the relative lifetimes of the signals. Tested on a two-layer memory hierarchy, this model led to savings of dynamic energy from 40% to over 70% relative to the energy used in the case of flat memory designs.</p>]]></description>
<dc:creator><![CDATA[ZHU, H., LUICAN, I. I., BALASA, F., PRADHAN, D. K.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3559</dc:identifier>
<dc:title><![CDATA[Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3567</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3559</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3568?rss=1">
<title><![CDATA[Optimal Common Sub-Expression Elimination Algorithm of Multiple Constant Multiplications with a Logic Depth Constraint]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3568?rss=1</link>
<description><![CDATA[<p>In the context of multiple constant multiplication (MCM) design, we propose a novel common sub-expression elimination (CSE) algorithm that models the optimal synthesis of coefficients into a 0-1 mixed-integer linear programming (MILP) problem with a user-defined generic logic depth constraint. We also propose an efficient solution space, which combines all minimal signed digit (MSD) representations and the shifted sum (difference) of coefficients. In the examples we demonstrate, the combination of the proposed algorithm and solution space gives a better solution comparing to existing algorithms.</p>]]></description>
<dc:creator><![CDATA[HO, Y.-H. A., LEI, C.-U., KWAN, H.-K., WONG, N.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3568</dc:identifier>
<dc:title><![CDATA[Optimal Common Sub-Expression Elimination Algorithm of Multiple Constant Multiplications with a Logic Depth Constraint]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3575</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3568</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3576?rss=1">
<title><![CDATA[Way-Scaling to Reduce Power of Cache with Delay Variation]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3576?rss=1</link>
<description><![CDATA[<p>The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (<I>V</I><SUB>th</SUB>) and/or gate-oxide thickness (<I>T</I><SUB>ox</SUB>) for cache transistors improves leakage, but impacts cell delay. We show that due to uncorrelated random within-die delay variation, only some (not all) of cells actually violate the cache delay after the above change. We propose to add a spare cache way to replace delay-violating cache-lines separately in each cache-set. By SPICE and gate-level simulations in a commercial 90 nm process, we show that choosing higher <I>V</I><SUB>th</SUB>, <I>T</I><SUB>ox</SUB> and adding one spare way to a 4-way 16 KB cache reduces leakage power by 42%, which depending on the share of leakage in total cache power, gives up to 22.59% and 41.37% reduction of total energy respectively in L1 instruction- and L2 unified-cache with a negligible delay penalty, but without sacrificing cache capacity or timing-yield.</p>]]></description>
<dc:creator><![CDATA[GOUDARZI, M., MATSUMURA, T., ISHIHARA, T.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3576</dc:identifier>
<dc:title><![CDATA[Way-Scaling to Reduce Power of Cache with Delay Variation]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3584</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3576</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3585?rss=1">
<title><![CDATA[Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3585?rss=1</link>
<description><![CDATA[<p>As well as the schedule affects system performance, the control skew, i.e., the arrival time difference of control signals between registers, can be utilized for improving the system performance, enhancing robustness against delay variations, etc. The simultaneous optimization of the control step assignment and the control skew assignment is more powerful technique in improving performance. In this paper, firstly, we prove that, even if the execution sequence of operations which are assigned to the same resource is fixed, the simultaneous optimization problem under a fixed clock period is <I>N</I>P-hard. Secondly, we propose a heuristic algorithm for the simultaneous control step and skew optimization under given clock period, and we show how much the simultaneous optimization improves system performance. This paper is the first one that uses the intentional skew to shorten control steps under a specified clock period. The proposed algorithm has the potential to play a central role in various scenarios of skew-aware high level synthesis.</p>]]></description>
<dc:creator><![CDATA[OBATA, T., KANEKO, M.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3585</dc:identifier>
<dc:title><![CDATA[Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3595</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3585</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3596?rss=1">
<title><![CDATA[Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3596?rss=1</link>
<description><![CDATA[<p>This paper presents a high-level synthesis approach to minimize the total power consumption in behavioral synthesis under time and area constraints. The proposed method has two stages, functional unit (FU) energy optimization and interconnect energy optimization. In the first stage, active and inactive energies of the FUs are optimized using a multiple supply and threshold voltage scheme. Genetic algorithm (GA) based simultaneous assignment of supply and threshold voltages and module selection is proposed. The proposed GA based searching method can be used in large size problems to find a near-optimal solution in a reasonable time. In the second stage, interconnects are simplified by increasing their sharing. This is done by exploiting similar data transfer patterns among FUs. The proposed method is evaluated for several benchmarks under 90 nm CMOS technology. The experimental results show that more than 40% of energy savings can be achieved by our proposed method.</p>]]></description>
<dc:creator><![CDATA[WAIDYASOORIYA, H. M., HARIYAMA, M., KAMEYAMA, M.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3596</dc:identifier>
<dc:title><![CDATA[Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3606</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3596</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3607?rss=1">
<title><![CDATA[Efficient Encoding Architecture for IEEE 802.16e LDPC Codes]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3607?rss=1</link>
<description><![CDATA[<p>The weakness of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which lead to limited throughput. In this letter in order to construct efficient architecture, we target on IEEE 802.16e LDPC encoders. Over the standard H matrices with Circulant Permutation Matrices, we propose semi-parallel architecture by using cyclic right shift registers and exclusive-OR instead of complex Matrix Vector Multipliers. Proposed efficient encoder for IEEE 802.16e LDPC satisfies compact size and high throughput.</p>]]></description>
<dc:creator><![CDATA[KIM, J. K., YOO, H., LEE, M. H.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3607</dc:identifier>
<dc:title><![CDATA[Efficient Encoding Architecture for IEEE 802.16e LDPC Codes]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3611</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3607</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Letters -- Embedded, Real-Time and Reconfigurable Systems</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3612?rss=1">
<title><![CDATA[Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3612?rss=1</link>
<description><![CDATA[<p>Recently, reconfigurable devices are widely used in the fields of small amount production and trial production. They are also expected to be utilized in such mission-critical fields as space development, because system update and pseudo-repair can be achieved remotely by reconfiguring. However, in the case of conventional reconfigurable devices, configuration memory upsets caused by radiation and alpha particles reconfigure the device unpredictably, resulting in fatal system failures. Therefore, a reconfigurable device with high fault-tolerance against configuration upsets is required. In this paper, we propose an architecture of a fault-tolerant reconfigurable device that autonomously repairs configuration upsets by itself without interrupting system operations. The device consists of a 2D array of "Autonomous-Repair Cells" each of which repairs its upsets autonomously. The architecture has a scalability in fault tolerance; a finer-grained Autonomous-Repair Cell provides higher fault-tolerance. To determine the architecture, we analyze four autonomous repair techniques of the cell experimentally. Then, two autonomous repair techniques, simple multiplexing (S.M.) and memory multiplexing (M.M.), are applied; the former to programmable logics and the latter to cell-to-cell routing resources. Through evaluation, we show that proposed device achieves more than 10 years average lifetime against configuration upsets even in a severe situation such as a satellite orbit.</p>]]></description>
<dc:creator><![CDATA[NAKAHARA, K., KOUYAMA, S., IZUMI, T., OCHI, H., NAKAMURA, Y.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3612</dc:identifier>
<dc:title><![CDATA[Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3621</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3612</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3622?rss=1">
<title><![CDATA[A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing Schedule]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3622?rss=1</link>
<description><![CDATA[<p>In this paper, we propose a partially-parallel irregular LDPC decoder based on IEEE 802.11n standard targeting high throughput and small area applications. The design is based on a novel sum-delta message passing algorithm characterized as follows: <b>(i)</b> Decoding throughput is greatly improved by utilizing the difference value between the updated and the original value to remove redundant computations. <b>(ii)</b> Registers and memory are optimized to store only the frequently used messages to decrease the hardware cost. <b>(iii)</b> Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5<FONT FACE="arial,helvetica">x</FONT> improvement in throughput, which reaches 402 Mbps at the frequency of 200 MHz, with 11% area reduction. The synthesis result also demonstrates the competitiveness to the fully-parallel regular LDPC decoders in terms of the tradeoff between throughput, area and power.</p>]]></description>
<dc:creator><![CDATA[JI, W., ABE, Y., IKENAGA, T., GOTO, S.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3622</dc:identifier>
<dc:title><![CDATA[A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing Schedule]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3629</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3622</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3630?rss=1">
<title><![CDATA[High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3630?rss=1</link>
<description><![CDATA[<p>Intra coding in H.264/AVC has significantly enhanced video compression efficiency. However, computation complexity increases by the rate-distortion (RD) based mode decision. This paper proposes a novel fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A novel edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce the number of intra 4 <FONT FACE="arial,helvetica">x</FONT> 4 candidate modes from 9 to an average of 2.50. VLSI architecture of intra mode decision module is designed with TSMC 0.18 &micro;m CMOS technology. The maximum frequency of 285 MHz is achieved and 13.1k NAND gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30 fps real time encoder.</p>]]></description>
<dc:creator><![CDATA[ZHANG, T., TIAN, G., IKENAGA, T., GOTO, S.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3630</dc:identifier>
<dc:title><![CDATA[High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3637</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3630</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3638?rss=1">
<title><![CDATA[Wide-Range Motion Estimation Architecture with Dual Search Windows or High Resolution Video Coding]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3638?rss=1</link>
<description><![CDATA[<p>This paper presents a memory-efficient motion estimation (ME) technique for high-resolution video compression. The main objective is to reduce the external memory access, especially for limited local memory resource. The reduction of memory access can successfully save the notorious power consumption. The key to reduce the memory accesses is based on center-biased algorithm in that the center-biased algorithm performs the motion vector (MV) searching with the minimum search data. While considering the data reusability, the proposed dual-search-windowing (DSW) approaches use the secondary windowing as an option per searching necessity. By doing so, the loading of search windows can be alleviated and hence reduce the required external memory bandwidth. The proposed techniques can save up to 81% of external memory bandwidth and require only 135 MBytes/sec, while the quality degradation is less than 0.2 dB for 720 p HDTV clips coded at 8 Mbits/sec.</p>]]></description>
<dc:creator><![CDATA[DUNG, L.-R., LIN, M.-C.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3638</dc:identifier>
<dc:title><![CDATA[Wide-Range Motion Estimation Architecture with Dual Search Windows or High Resolution Video Coding]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3650</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3638</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3651?rss=1">
<title><![CDATA[Area-Efficient Reconfigurable Architecture for Media Processing]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3651?rss=1</link>
<description><![CDATA[<p>An area-efficient dynamically reconfigurable architecture is proposed, which is dedicated to media processing. To implement a compact but high performance device, which can be used in consumer applications, the reconfigurable architecture distinctively performs 8-bit operations required for media processing whereas fine-grained operations are executed with the cooperation of a host processor. A heterogeneous reconfigurable array is composed of four types of cells, for which configuration data size is reduced by focusing application domain on media processing. Implementation results show that a multi-standard video decoding can be achieved by the proposed reconfigurable architecture with 1.1 <FONT FACE="arial,helvetica">x</FONT> 1.4 mm<sup>2</sup> in a 90 nm CMOS technology.</p>]]></description>
<dc:creator><![CDATA[MITSUYAMA, Y., TAKAHASHI, K., IMAI, R., HASHIMOTO, M., ONOYE, T., SHIRAKAWA, I.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3651</dc:identifier>
<dc:title><![CDATA[Area-Efficient Reconfigurable Architecture for Media Processing]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3662</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3651</prism:startingPage>
<prism:section>Special Section on VLSI Design and CAD Algorithms -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3663?rss=1">
<title><![CDATA[Special Section on Signal Design and its Application in Communications]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3663?rss=1</link>
<description><![CDATA[]]></description>
<dc:creator><![CDATA[Fan, P., Suehiro, N.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3663</dc:identifier>
<dc:title><![CDATA[Special Section on Signal Design and its Application in Communications]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3664</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3663</prism:startingPage>
<prism:section>Special Section on Signal Design and its Application in Communications</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3665?rss=1">
<title><![CDATA[On Almost Perfect Nonlinear Functions]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3665?rss=1</link>
<description><![CDATA[<p>A function <I>F</I>:F<SUB>2</SUB><sup><I>n</I></sup> -&gt; F<SUB>2</SUB><sup><I>n</I></sup> is <I>almost perfect nonlinear</I> (APN) if, for every <I>a</I> != 0, <I>b</I> in F<SUB>2</SUB><sup><I>n</I></sup>, the equation <I>F</I>(<I>x</I>) + <I>F</I>(<I>x</I> + <I>a</I>) = <I>b</I> has at most two solutions in F<SUB>2</SUB><sup><I>n</I></sup>. When used as an S-box in a block cipher, it contributes optimally to the resistance to differential cryptanalysis. The function <I>F</I> is <I>almost bent</I> (AB) if the minimum Hamming distance between all its <I>component</I> functions <I>v</I> &middot; <I>F</I>, <I>v</I>  F<SUB>2</SUB><sup><I>n</I></sup> \ {0} (where "&middot;" denotes any inner product in F<SUB>2</SUB><sup><I>n</I></sup>) and all affine Boolean functions on F<SUB>2</SUB><sup><I>n</I></sup> takes the maximal value 2<sup><I>n</I>&ndash;1</sup> &ndash; 2 <sup><I>n</I> &ndash; 1/2</sup>. AB functions exist for <I>n</I> odd only and contribute optimally to the resistance to the linear cryptanalysis. Every AB function is APN, and in the <I>n</I> odd case, any quadratic APN function is AB. The APN and AB properties are preserved by affine equivalence: <I>F</I> ~ <I>F'</I> if <I>F'</I> = <I>A</I><SUB>1</SUB>  <I>F</I>  <I>A</I><SUB>2</SUB>, where <I>A</I><SUB>1</SUB>,<I>A</I><SUB>2</SUB> are affine permutations. More generally, they are preserved by CCZ-equivalence, that is, affine equivalence of the graphs of <I>F</I>: {(<I>x,F(x)</I>) | <I>x</I>  F<SUB>2</SUB><sup><I>n</I></sup>} and of <I>F'</I>. Until recently, the only known constructions of APN and AB functions were CCZ-equivalent to power functions <I>F(x)</I> = <I>x<sup>d</sup></I> over finite fields (F<SUB>2</SUB><sup><I>n</I></sup> being identified with F<SUB>2</SUB><sup><I>n</I></sup> and an inner product being <I>x &middot; y</I> = <I>tr(xy)</I> where <I>tr</I> is the trace function). Several recent infinite classes of APN functions have been proved CCZ-inequivalent to power functions. In this paper, we describe the state of the art in the domain and we also present original results. We indicate what are the most important open problems and make some new observations about them. Many results presented are from joint works with Lilya Budaghyan, Gregor Leander and Alexander Pott.</p>]]></description>
<dc:creator><![CDATA[CARLET, C.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3665</dc:identifier>
<dc:title><![CDATA[On Almost Perfect Nonlinear Functions]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3678</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3665</prism:startingPage>
<prism:section>Special Section on Signal Design and its Application in Communications -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3679?rss=1">
<title><![CDATA[Autocorrelation of Some Quaternary Cyclotomic Sequences of Length 2p]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3679?rss=1</link>
<description><![CDATA[<p>We define a new quaternary cyclotomic sequences of length 2<I>p</I>, where <I>p</I> is an odd prime. We compute the autocorrelation of these sequences. In terms of magnitude, these sequences have the autocorrelations with at most 4 values.</p>]]></description>
<dc:creator><![CDATA[KIM, Y.-J., HONG, Y.-P., SONG, H.-Y.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3679</dc:identifier>
<dc:title><![CDATA[Autocorrelation of Some Quaternary Cyclotomic Sequences of Length 2p]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3684</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3679</prism:startingPage>
<prism:section>Special Section on Signal Design and its Application in Communications -- Papers -- Nonlinear Problems</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3685?rss=1">
<title><![CDATA[Generalized M-Ary Related-Prime Sequences with Low Correlation]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3685?rss=1</link>
<description><![CDATA[<p>In this paper we introduce new <I>M</I>-ary sequences of length <I>pq</I>, called <I>generalized M-ary related-prime sequences</I>, where <I>p</I> and <I>q</I> are distinct odd primes, and <I>M</I> is a common divisor of <I>p</I> &ndash; 1 and <I>q</I> &ndash; 1. We show that their out-of-phase autocorrelation values are upper bounded by the maximum between <I>q &ndash; p</I> + 1 and 5. We also construct a family of generalized <I>M</I>-ary related-prime sequences and show that the maximum correlation of the proposed sequence family is upper bounded by <I>p + q</I> &ndash; 1.</p>]]></description>
<dc:creator><![CDATA[HAN, Y. K., YANG, K.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3685</dc:identifier>
<dc:title><![CDATA[Generalized M-Ary Related-Prime Sequences with Low Correlation]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3690</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3685</prism:startingPage>
<prism:section>Special Section on Signal Design and its Application in Communications -- Papers -- Sequence</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3691?rss=1">
<title><![CDATA[New Families of Optimal Zero Correlation Zone Sequences Based on Interleaved Technique and Perfect Sequences]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3691?rss=1</link>
<description><![CDATA[<p>In this paper, based on interleaved technique, we present a new method of constructing zero correlation zone (ZCZ) sequence sets. For any perfect sequence of length <I>m</I>(2<I>k</I> + 1) with <I>m</I> &gt; 2, <I>k</I> &ge; 0 and an arbitrary Hadamard matrix of order <I>T</I> &gt; 2, the proposed construction can generate new optimal ZCZ sequence sets in which all the sequences are cyclically distinct.</p>]]></description>
<dc:creator><![CDATA[ZHOU, Z., PAN, Z., TANG, X.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3691</dc:identifier>
<dc:title><![CDATA[New Families of Optimal Zero Correlation Zone Sequences Based on Interleaved Technique and Perfect Sequences]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3697</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3691</prism:startingPage>
<prism:section>Special Section on Signal Design and its Application in Communications -- Papers -- Sequence</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3698?rss=1">
<title><![CDATA[A New Construction Method of Zero-Correlation Zone Sequences Based on Complete Complementary Codes]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3698?rss=1</link>
<description><![CDATA[<p>In approximately synchronous CDMA (AS-CDMA) systems, zero correlation zone (ZCZ) sequences are known as the sequences to eliminate co-channel and multi-path interferences. Therefore, numerous constructions of zero correlation zone (ZCZ) sequences have been introduced e.g. based on perfect sequences and complete complementary codes etc. However, the previous construction method which based on complete complementary code is lacking for merit figures when none of whose elements are zero. In this paper, a new construction method of ZCZ sequences based on complete complementary codes is proposed. By proposed method, non zero elements ZCZ sequences whose merit figure is greater than 1/2 are constructable.</p>]]></description>
<dc:creator><![CDATA[HAN, C., HASHIMOTO, T., SUEHIRO, N.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3698</dc:identifier>
<dc:title><![CDATA[A New Construction Method of Zero-Correlation Zone Sequences Based on Complete Complementary Codes]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3702</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3698</prism:startingPage>
<prism:section>Special Section on Signal Design and its Application in Communications -- Papers -- Sequence</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3703?rss=1">
<title><![CDATA[Construction and Performance Analysis of OVSF-ZCZ Codes Based on LS and GO Sequences]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3703?rss=1</link>
<description><![CDATA[<p>Zero Correlation Zone (ZCZ) sequences have been confirmed the capability in interference mitigation in multipath fading channel. On the other hand, Orthogonal Variable Spreading Factor (OVSF) codes have been successfully applied in WCDMA for separating different channels with different transmission capacity. In this paper, novel OVSF-ZCZ sequences originated from LS and GO sequences have been proposed for CDMA systems with different service requirements. The construction method is discussed and the performance of the system is evaluated.</p>]]></description>
<dc:creator><![CDATA[ZHANG, C., TAO, X., LU, J.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3703</dc:identifier>
<dc:title><![CDATA[Construction and Performance Analysis of OVSF-ZCZ Codes Based on LS and GO Sequences]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3711</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3703</prism:startingPage>
<prism:section>Special Section on Signal Design and its Application in Communications -- Papers -- Sequence</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3712?rss=1">
<title><![CDATA[Adaptive CI-OSDM in Time-Frequency Selective Fading Channel]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3712?rss=1</link>
<description><![CDATA[<p>Orthogonal Signal Division Multiplexing (OSDM), also known as SD-OFDM, has been proposed for information transmission with high spectrum efficiency. In this paper, a new signal construction method named Adaptive Carrier Interferometry OSDM (ACI-OSDM) is proposed for time-frequency selective fading channel. Particularly, the Adaptive CI codes originated from CI-OFDM are employed in the frequency domain of OSDM signal. Compared with traditional OFDM, the ACI-OSDM improves the performance considerably of broadband transmission, i.e., spectrum efficiency, Peak-to-Average Power Ratio (PAPR) mitigation and interference cancelation in the high speed mobile environment with multipath emission, e.g. super express train with speed more than 250 km/h.</p>]]></description>
<dc:creator><![CDATA[TAO, X., ZHANG, C., LU, J., SUEHIRO, N.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3712</dc:identifier>
<dc:title><![CDATA[Adaptive CI-OSDM in Time-Frequency Selective Fading Channel]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3722</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3712</prism:startingPage>
<prism:section>Special Section on Signal Design and its Application in Communications -- Papers -- Spread Spectrum Communications</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3723?rss=1">
<title><![CDATA[Multitone-Hopping CDMA Using Feedback-Controlled Hopping Pattern for Decentralized Multiple Access]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3723?rss=1</link>
<description><![CDATA[<p>We propose multitone-hopping code-division multiple access (MH-CDMA) using a feedback-controlled hopping pattern (FCHP) (FCHP/MH-CDMA). In the FCHP/MH-CDMA, part of the filter coefficients of an adaptive finite-duration impulse response (FIR) filter receiver are fed back to a transmitter, in which they are used as an updated hopping pattern. Each chip of the updated hopping pattern consists of plural tones. As a result, it is shown that the FCHP/MH-CDMA provides us with an excellent asynchronous, decentralized multiple-access performance over time-invariant multipath channels.</p>]]></description>
<dc:creator><![CDATA[CHIBA, K., HAMAMURA, M.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3723</dc:identifier>
<dc:title><![CDATA[Multitone-Hopping CDMA Using Feedback-Controlled Hopping Pattern for Decentralized Multiple Access]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3730</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3723</prism:startingPage>
<prism:section>Special Section on Signal Design and its Application in Communications -- Papers -- Spread Spectrum Communications</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3731?rss=1">
<title><![CDATA[Some Upper Bounds on the Inverse Relative Dimension/Length Profile]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3731?rss=1</link>
<description><![CDATA[<p>The generalized Hamming weight played an important role in coding theory. In the study of the wiretap channel of type II, the generalized Hamming weight was extended to a two-code format. Two equivalent concepts of the generalized Hamming weight hierarchy and its two-code format, are the inverse dimension/length profile (IDLP) and the inverse relative dimension/length profile (IRDLP), respectively. In this paper, the Singleton upper bound on the IRDLP is improved by using a quotient subcode set and a subset with respect to a generator matrix, respectively. If these new upper bounds on the IRDLP are achieved, in the corresponding coordinated two-party wire-tap channel of type II, the adversary cannot learn more from the illegitimate party.</p>]]></description>
<dc:creator><![CDATA[WANG, P., LUO, Y., VINCK, A.J. H.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3731</dc:identifier>
<dc:title><![CDATA[Some Upper Bounds on the Inverse Relative Dimension/Length Profile]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3737</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3731</prism:startingPage>
<prism:section>Special Section on Signal Design and its Application in Communications -- Papers -- Coding Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3738?rss=1">
<title><![CDATA[Design of a Fuzzy Based Outer Loop Controller for Improving the Training Performance of LMS Algorithm]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3738?rss=1</link>
<description><![CDATA[<p>Because of the fact that mobile communication channel changes by time, it is necessary to employ adaptive channel equalizers in order to combat the distorting effects of the channel. Least Mean Squares (LMS) algorithm is one of the most popular channel equalization algorithms and is preferred over other algorithms such as the Recursive Least Squares (RLS) and Maximum Likelihood Sequence Estimation (MLSE) when simplicity is the dominant decision factor. However, LMS algorithm suffers from poor performance and convergence speed within the training period specified by most of the standards. The aim of this study is to improve the convergence speed and performance of the LMS algorithm by adjusting the step size using fuzzy logic. The proposed method is compared with the Channel Matched Filter-Decision Feedback Equalizer (CMF-DFE) [1] which provides multi path propagation diversity by collecting the energy in the channel, Minimum Mean Square Error-Decision Feedback Equalizer (MMSE-DFE) [2] which is one of the most successful equalizers for the data packet transmission, normalized LMS-DFE (N-LMS-DFE) [3], variable step size (VSS) LMS-DFE [4], fuzzy LMS-DFE [5],[6] and RLS-DFE [7]. The obtained simulation results using HIPERLAN/1 standards have demonstrated that the proposed LMS-DFE algorithm based on fuzzy logic has considerably better performance than others.</p>]]></description>
<dc:creator><![CDATA[OZEN, A., KAYA, I., SOYSAL, B.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3738</dc:identifier>
<dc:title><![CDATA[Design of a Fuzzy Based Outer Loop Controller for Improving the Training Performance of LMS Algorithm]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3744</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3738</prism:startingPage>
<prism:section>Special Section on Signal Design and its Application in Communications -- Papers -- Channel Equalization</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3745?rss=1">
<title><![CDATA[Zero Correlation Distribution of ZCZ Sequences Obtained from a Perfect Sequence and a Unitary Matrix]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3745?rss=1</link>
<description><![CDATA[<p>A class of zero-correlation zone (ZCZ) sequences constructed by the recursive procedure from a perfect sequence and a unitary matrix was proposed by Torii, Nakamura, and Suehiro [1]. In the reference [1], three parameters, s.t., the sequence length, the family size and the length of the ZCZ, were evaluated for a general estimate of the performance of the ZCZ sequences. In this letter, we give more detailed distributions of that correlation values are zero on their ZCZ sequence sets.</p>]]></description>
<dc:creator><![CDATA[UEHARA, S., JONO, S., NOGAMI, Y.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3745</dc:identifier>
<dc:title><![CDATA[Zero Correlation Distribution of ZCZ Sequences Obtained from a Perfect Sequence and a Unitary Matrix]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3748</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3745</prism:startingPage>
<prism:section>Special Section on Signal Design and its Application in Communications -- Letter -- Sequence</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3749?rss=1">
<title><![CDATA[Motion Planning of Bimanual Robot Using Adaptive Model of Assembly]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3749?rss=1</link>
<description><![CDATA[<p>This paper presents a motion planning method for a bimanual robot for executing assembly tasks. The method employs an adaptive modeling which can automatically generate an assembly model and modify the model during actual assembly. Bimanual robotic assembly is modeled at the task-level using contact states of workpieces and their transitions. The lower-level velocity commands of the workpieces are automatically derived by solving optimization problem formulated with assembly constraints, position of the workpieces, and kinematics of manipulators. Motion requirements of the workpieces are transformed to motion commands of the bimanual robot. The proposed approach is evaluated with experiments on peg-in-hole assembly with an L-shaped peg.</p>]]></description>
<dc:creator><![CDATA[HWANG, M. J., LEE, D. Y., CHUNG, S. Y.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3749</dc:identifier>
<dc:title><![CDATA[Motion Planning of Bimanual Robot Using Adaptive Model of Assembly]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3756</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3749</prism:startingPage>
<prism:section>Regular Section -- Papers -- Systems and Control</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3757?rss=1">
<title><![CDATA[Fast Simulation Technique of Plane Circuits via Two-Layer CNN-Based Modeling]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3757?rss=1</link>
<description><![CDATA[<p>A fast time-domain simulation technique of plane circuits via two-layer Cellular Neural Network (CNN)-based modeling, which is necessary for power/signal integrity evaluation in VLSIs, printed circuit boards, and packages, is presented. Using the new notation expressed by the two-layer CNN, 1,553 times faster simulation is achieved, compared with Berkeley SPICE (<I>ngspice</I>). In CNN community, CNNs are generally simulated by explicit numerical integration such as the forward Euler and Runge-Kutta methods. However, since the two-layer CNN is a stiff circuit, we cannot analyze it by using an explicit numerical integration method. Hence, to analyze the two-layer CNN and reduce the computational cost, the leapfrog method is introduced. This procedure would open an application of CNN to electronic design automation area.</p>]]></description>
<dc:creator><![CDATA[TANJI, Y., ASAI, H., ODA, M., NISHIO, Y., USHIDA, A.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3757</dc:identifier>
<dc:title><![CDATA[Fast Simulation Technique of Plane Circuits via Two-Layer CNN-Based Modeling]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3762</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3757</prism:startingPage>
<prism:section>Regular Section -- Papers -- Nonlinear Problems</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3763?rss=1">
<title><![CDATA[Broadband Equalizer Design with Commensurate Transmission Lines via Reflectance Modeling]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3763?rss=1</link>
<description><![CDATA[<p>In this paper, an alternative approach is presented, to design equalizers (or matching networks) with commensurate (or equal length) transmission lines. The new method automatically yields the matching network topology with characteristic impedances of the commensurate lines. In the implementation process of the new technique first, the driving point impedance data of the matching network is generated by tracing a pre-selected transducer power gain shape, without optimization. Then, it is modelled as a realizable bounded-real input reflection coefficient in Richard domain, which in turn yields the desired equalizer topology with line characteristic impedances. This process results in an excellent initial design for the commercially available computer aided design (CAD) packages to generate final circuit layout for fabrication. An example is given to illustrate the utilization of the new method. It is expected that the proposed design technique is employed as a front-end, to commercially available computer aided design (CAD) packages which generate the actual equalizer circuit layout with physical dimensions for mass production.</p>]]></description>
<dc:creator><![CDATA[SENGUL, M., YARMAN, S. B.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3763</dc:identifier>
<dc:title><![CDATA[Broadband Equalizer Design with Commensurate Transmission Lines via Reflectance Modeling]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3771</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3763</prism:startingPage>
<prism:section>Regular Section -- Papers -- Circuit Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3772?rss=1">
<title><![CDATA[A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3772?rss=1</link>
<description><![CDATA[<p>An algorithm for clock scheduling of concurrent-flow clocking rapid single-flux-quantum (RSFQ) digital circuits is proposed. RSFQ circuit technology is an emerging technology of digital circuits. In concurrent-flow clocking RSFQ digital circuits, all logic gates are driven by clock pulses. Appropriate clock scheduling makes clock frequency of the circuits higher. Given a clock period, the proposed algorithm determines the arrival time of clock pulses and the delay that should be inserted. Experimental results show that inserted delay elements by the proposed algorithm are 59.0% fewer and the height of clock trees are 40.4% shorter on average than those by a straightforward algorithm. The proposed algorithm can also be used to minimize the clock period, thus obtaining 19.0% shorter clock periods on average.</p>]]></description>
<dc:creator><![CDATA[OBATA, K., TAKAGI, K., TAKAGI, N.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3772</dc:identifier>
<dc:title><![CDATA[A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3782</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3772</prism:startingPage>
<prism:section>Regular Section -- Papers -- VLSI Design Technology and CAD</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3783?rss=1">
<title><![CDATA[Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3783?rss=1</link>
<description><![CDATA[<p>This paper studies the impact of dummy fill for chemical mechanical polishing (CMP)-induced capacitance variation on buffer insertion based on a virtual CMP fill estimation model. Compared with existing methods, our algorithm is more feasible by performing buffer insertion not in post-process but during early physical design. Our contributions are threefold. First, we introduce an improved fast dummy fill amount estimation algorithm based on [4], and use some speedup techniques (tile merging, fill factor and amount assigning) for early estimation. Second, based on some reasonable assumptions, we present an optimum virtual dummy fill method to estimate dummy position and the effect on the interconnect capacitance. Then the dummy fill estimation model was verified by our experiments. Third, we use this model in early buffer insertion after layer assignment considering the effects of dummy fill. Experimental results verified the necessity of early dummy fill estimation and the validity of our algorithm. Buffer insertion considering dummy fill during early physical design is necessary and our algorithm is promising.</p>]]></description>
<dc:creator><![CDATA[JIA, Y., CAI, Y., HONG, X.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3783</dc:identifier>
<dc:title><![CDATA[Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3792</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3783</prism:startingPage>
<prism:section>Regular Section -- Papers -- VLSI Design Technology and CAD</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3793?rss=1">
<title><![CDATA[DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3793?rss=1</link>
<description><![CDATA[<p>Recently much attention has been paid to quantum circuit design to prepare for the future "quantum computation era." Like the conventional logic synthesis, it should be important to verify and analyze the functionalities of generated quantum circuits. For that purpose, we propose an efficient verification method for quantum circuits under a practical restriction. Thanks to the restriction, we can introduce an efficient verification scheme based on decision diagrams called <I>Decision Diagrams for Matrix Functions (DDMFs)</I>. Then, we show analytically the advantages of our approach based on DDMFs over the previous verification techniques. In order to introduce DDMFs, we also introduce new concepts, <I>quantum functions</I> and <I>matrix functions</I>, which may also be interesting and useful on their own for designing quantum circuits.</p>]]></description>
<dc:creator><![CDATA[YAMASHITA, S., MINATO, S.-i., MILLER, D. M.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3793</dc:identifier>
<dc:title><![CDATA[DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3802</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3793</prism:startingPage>
<prism:section>Regular Section -- Papers -- VLSI Design Technology and CAD</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3803?rss=1">
<title><![CDATA[A Fast Clock Scheduling for Peak Power Reduction in LSI]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3803?rss=1</link>
<description><![CDATA[<p>The reduction of the peak power consumption of LSI is required to reduce the instability of gate operation, the delay increase, the noise, and etc. It is possible to reduce the peak power consumption by clock scheduling because it controls the switching timings of registers and combinational logic elements. In this paper, we propose a fast peak power wave estimation method for clock scheduling and fast clock scheduling methods for the peak power reduction. In experiments, it is shown that the peak power wave estimated by the proposed method in a few seconds is highly correlated with the peak power wave obtained by HSPICE simulation in several days. By using the proposed peak power wave estimation method, proposed clock scheduling methods find clock schedules that greatly reduce the peak power consumption in a few minutes.</p>]]></description>
<dc:creator><![CDATA[TAKAHASHI, Y., KOHIRA, Y., TAKAHASHI, A.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3803</dc:identifier>
<dc:title><![CDATA[A Fast Clock Scheduling for Peak Power Reduction in LSI]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3811</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3803</prism:startingPage>
<prism:section>Regular Section -- Papers -- VLSI Design Technology and CAD</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3812?rss=1">
<title><![CDATA[Speech Enhancement Using Improved Adaptive Null-Forming in Frequency Domain with Postfilter]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3812?rss=1</link>
<description><![CDATA[<p>In this letter, a two channel frequency domain speech enhancement algorithm is proposed. The algorithm is designed to achieve better overall performance with relatively small array size. An improved version of adaptive null-forming is used, in which noise cancelation is implemented in auditory subbands. And an OM-LSA based postfiltering stage further purifies the output. The algorithm also features interaction between the array processing and the postfilter to make the filter adaptation more robust. This approach achieves considerable improvement on signal-to-noise ratio (SNR) and subjective quality of the desired speech. Experiments confirm the effectiveness of the proposed system.</p>]]></description>
<dc:creator><![CDATA[ZHANG, H., FU, Q., YAN, Y.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3812</dc:identifier>
<dc:title><![CDATA[Speech Enhancement Using Improved Adaptive Null-Forming in Frequency Domain with Postfilter]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3816</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3812</prism:startingPage>
<prism:section>Regular Section -- Letters -- Speech and Hearing</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3817?rss=1">
<title><![CDATA[Rank M-Type L (RM L)-Filter for Image Denoising]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3817?rss=1</link>
<description><![CDATA[<p>We introduce the Rank M-type L (RM L) -filter to remove impulsive and speckle noise from corrupted images by means of use of DSP TMS320C6701.</p>]]></description>
<dc:creator><![CDATA[GALLEGOS-FUNES, F., VARELA-BENITEZ, J., PONOMARYOV, V.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3817</dc:identifier>
<dc:title><![CDATA[Rank M-Type L (RM L)-Filter for Image Denoising]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3819</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3817</prism:startingPage>
<prism:section>Regular Section -- Letters -- Digital Signal Processing</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3820?rss=1">
<title><![CDATA[Affine Projection Algorithm with Improved Data-Selective Method Using the Condition Number]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3820?rss=1</link>
<description><![CDATA[<p>Recently, a data-selective method has been proposed to achieve low misalignment in affine projection algorithm (APA) by keeping the condition number of an input data matrix small. We present an improved method, and a complexity reduction algorithm for the APA with the data-selective method. Experimental results show that the proposed algorithm has lower misalignment and a lower condition number for an input data matrix than both the conventional APA and the APA with the previous data-selective method.</p>]]></description>
<dc:creator><![CDATA[BAN, S. J., LEE, C. W., KIM, S. W.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3820</dc:identifier>
<dc:title><![CDATA[Affine Projection Algorithm with Improved Data-Selective Method Using the Condition Number]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3823</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3820</prism:startingPage>
<prism:section>Regular Section -- Letters -- Digital Signal Processing</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3824?rss=1">
<title><![CDATA[Constrained Total Least-Squares Algorithm for Hyperbolic Location]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3824?rss=1</link>
<description><![CDATA[<p>A novel algorithm for source location by utilizing the time-difference-of-arrival (TDOA) of a signal received at spatially separated sensors is proposed. The algorithm is based on the constrained total least-squares (CTLS) technique and gives an explicit solution. Simulation results demonstrate that the proposed algorithm has high location accuracy and its performance is close to the Cramer-Rao lower bound (CRLB).</p>]]></description>
<dc:creator><![CDATA[YANG, K., AN, J., BU, X., XU, Z.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3824</dc:identifier>
<dc:title><![CDATA[Constrained Total Least-Squares Algorithm for Hyperbolic Location]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3827</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3824</prism:startingPage>
<prism:section>Regular Section -- Letters -- Digital Signal Processing</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3828?rss=1">
<title><![CDATA[Anonymous Identity Based Encryption with Plaintext Awareness in the Two Identities Setting]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3828?rss=1</link>
<description><![CDATA[<p>An <I>anonymous</I> identity based encryption (anonymous IBE) scheme requires that an adversary can not determine the identity of the recipient from a ciphertext encrypted by the corresponding public key. The anonymity was formalized in previous works [1],[13], and this can be considered under chosen plaintext attack and adaptive chosen ciphertext attack, yielding two notions of security, ID-II-CPA and ID-II-CCA, where II denotes "indistinguishability of identities." However, how to obtain an ID-II-CCA secure anonymous IBE in the random oracle model is still a challenging problem. We firstly propose a new notion of plaintext awareness in the two identities setting, called PATI. Secondly, we prove that the IBE scheme is ID-II-CCA secure if it is PATI secure. Finally, we propose the first generic conversion for anonymous IBE from ID-II-CPA to ID-II-CCA in the random oracle model.</p>]]></description>
<dc:creator><![CDATA[LIN, C., LI, Y., ZHANG, Q., YE, D.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3828</dc:identifier>
<dc:title><![CDATA[Anonymous Identity Based Encryption with Plaintext Awareness in the Two Identities Setting]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3832</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3828</prism:startingPage>
<prism:section>Regular Section -- Letters -- Cryptography and Information Security</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3833?rss=1">
<title><![CDATA[Identity-Based Authenticated Key Agreement Protocols without Bilinear Pairings]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3833?rss=1</link>
<description><![CDATA[<p>This letter proposes an identity-based authenticated key agreement protocol. Different from available comparable ones, the new protocol realizes implicit authentication without bilinear pairings which makes it more efficient. The security of proposed protocol can be reduced to the standard Computational Diffie-Hellman problem. Two variants of the protocol are also given, with one achieving the security-efficiency trade-off and the other providing authenticated key agreement between users of different domains.</p>]]></description>
<dc:creator><![CDATA[CAO, X., KOU, W., YU, Y., SUN, R.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3833</dc:identifier>
<dc:title><![CDATA[Identity-Based Authenticated Key Agreement Protocols without Bilinear Pairings]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3836</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3833</prism:startingPage>
<prism:section>Regular Section -- Letters -- Cryptography and Information Security</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3837?rss=1">
<title><![CDATA[Cryptanalysis and Enhancement of Modified Gateway-Oriented Password-Based Authenticated Key Exchange Protocol]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3837?rss=1</link>
<description><![CDATA[<p>Abdalla et al. proposed a gateway-oriented password-based authenticated key exchange (GPAKE) protocol among a client, a gateway, and an authentication server, where a password is only shared between the client and the authentication server. The goal of their scheme is to securely establish a session key between the client and the gateway by the help of the authentication server without revealing any information on the password to the gateway. Recently, Byun et al. showed that Abdalla et al.'s GPAKE is insecure against undetectable on-line password guessing attacks. They also proposed a modified version to overcome the attacks. In this letter, we point out that Byun et al.'s modified GPAKE protocol is still insecure against the same attacks. We then make a suggestion for improvement.</p>]]></description>
<dc:creator><![CDATA[SHIM, K.-A.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3837</dc:identifier>
<dc:title><![CDATA[Cryptanalysis and Enhancement of Modified Gateway-Oriented Password-Based Authenticated Key Exchange Protocol]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3839</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3837</prism:startingPage>
<prism:section>Regular Section -- Letters -- Cryptography and Information Security</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3840?rss=1">
<title><![CDATA[Low-Complexity Post-FFT Fine Frequency Synchronization for OFDM]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3840?rss=1</link>
<description><![CDATA[<p>In this letter, we suggest a simple way of implementing a post-FFT pilot-assisted sampling frequency offset and residual frequency offset estimator with reduced complexity in an orthogonal frequency division multiplexing (OFDM) system. In order to devise the low-complexity post-FFT frequency estimator, some modifications on the conventional estimator are highlighted with an emphasis on the selection of pilot subset.</p>]]></description>
<dc:creator><![CDATA[YOU, Y.-H., KANG, S.-J., SONG, H.-K.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3840</dc:identifier>
<dc:title><![CDATA[Low-Complexity Post-FFT Fine Frequency Synchronization for OFDM]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3842</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3840</prism:startingPage>
<prism:section>Regular Section -- Letters -- Communication Theory and Signals</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3843?rss=1">
<title><![CDATA[A Novel View of Color-Based Visual Tracker Using Principal Component Analysis]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3843?rss=1</link>
<description><![CDATA[<p>An extension of the traditional color-based visual tracker, i.e., the continuously adaptive mean shift tracker, is given for improving the convenience and generality of the color-based tracker. This is achieved by introducing a probability density function for pixels based on the hue histogram of object. As its merits, the direction and size of the tracked object are easily derived by the principle component analysis (PCA), and its extension to three-dimensional case becomes straightforward.</p>]]></description>
<dc:creator><![CDATA[NISHIYAMA, K., LU, X.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3843</dc:identifier>
<dc:title><![CDATA[A Novel View of Color-Based Visual Tracker Using Principal Component Analysis]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3848</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3843</prism:startingPage>
<prism:section>Regular Section -- Letters -- Vision</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3849?rss=1">
<title><![CDATA[Measures of End-User Information Competency in an Organizational Information Environment]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/12/3849?rss=1</link>
<description><![CDATA[<p>Efficient use of information technology (IT) is considered a major determinant of an end-user's business performance and an enterprise's competitiveness. A 16-item tool that can efficiently measure end-user information competency is presented with the measures. The validity and reliability of the tool is confirmed, and the tool's theoretical and practical applications are discussed.</p>]]></description>
<dc:creator><![CDATA[YOON, C. Y.]]></dc:creator>
<dc:date>2008-12-22</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.12.3849</dc:identifier>
<dc:title><![CDATA[Measures of End-User Information Competency in an Organizational Information Environment]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>12</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3853</prism:endingPage>
<prism:publicationDate>2008-12-01</prism:publicationDate>
<prism:startingPage>3849</prism:startingPage>
<prism:section>Regular Section -- Letters -- Language, Thought, Knowledge and Intelligence</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3093?rss=1">
<title><![CDATA[Special Section on Wideband Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3093?rss=1</link>
<description><![CDATA[]]></description>
<dc:creator><![CDATA[Kobayashi, T.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3093</dc:identifier>
<dc:title><![CDATA[Special Section on Wideband Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3094</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3093</prism:startingPage>
<prism:section>Special Section on Wideband Systems</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3095?rss=1">
<title><![CDATA[Blind Channel Shortening for Block Transmission of Correlated Signals]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3095?rss=1</link>
<description><![CDATA[<p>In block transmission systems, blind channel shortening methods are known to be effective to reduce the influence of interblock interference which degrades the performance when the length of a channel impulse response is extremely long. Conventional methods assume that the transmitted signal is uncorrelated; however, this assumption is invalid in practical systems such as OFDM with null carriers and MC-CDMA. In this paper, we consider blind channel shortening methods for block transmissions when the transmitted samples within a block are correlated. First, the channel shortening ability of a conventional method is clarified. Next, a new method which exploits the fact that the transmitted samples in different blocks are uncorrelated is introduced. It is shown that the proposed method can shorten the channel properly under certain conditions. Finally, simulation results of OFDM and MC-CDMA systems are shown to verify the effectiveness of the proposed method compared with a conventional one.</p>]]></description>
<dc:creator><![CDATA[MIYAJIMA, T., WATANABE, Y.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3095</dc:identifier>
<dc:title><![CDATA[Blind Channel Shortening for Block Transmission of Correlated Signals]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3103</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3095</prism:startingPage>
<prism:section>Special Section on Wideband Systems -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3104?rss=1">
<title><![CDATA[Multipath Diversity through Time Shifted Sampling for Spatially Correlated OFDM-Antenna Array Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3104?rss=1</link>
<description><![CDATA[<p>An essential condition for diversity reception is that the fading distributions between individual received signals of an antenna array are uncorrelated. In this paper, a new technique to improve the performance of transmission with the correlated Rayleigh-fading signals is proposed. In conventional array systems, individual receivers start sampling the received signals at the same time with the same sampling rate. On the other hand, in the proposed scheme, the received signals are again sampled with the same rate, however the sampling points are shifted in each receiver. Numerical results through computer simulation show that with correlated received signals, by applying the proposed technique the correlation can be reduced to a sufficient level for diversity reception.</p>]]></description>
<dc:creator><![CDATA[KIZILIRMAK, R. C., SANADA, Y.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3104</dc:identifier>
<dc:title><![CDATA[Multipath Diversity through Time Shifted Sampling for Spatially Correlated OFDM-Antenna Array Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3111</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3104</prism:startingPage>
<prism:section>Special Section on Wideband Systems -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3112?rss=1">
<title><![CDATA[Joint Use of Adaptive Equalization and Cyclic Noise Cancellation for Band-Limited OQAM Based Multi-Carrier Transmission in Power-Line Communication Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3112?rss=1</link>
<description><![CDATA[<p>Power-line communication (PLC) technique is one method to realize high-speed communications in a home network. In PLC channels, the transmission signal quality is degraded by colored non-Gaussian noise as well as frequency-selectivity of the channels. In this paper, we describe our investigation of the performance of a OQAM-MCT system in which a noise canceller is used jointly with a time-domain per-subcarrier adaptive equalizer. Furthermore, we propose a noise cancellation method designed for the OQAM-MCT system. The performance of the OQAM-MCT system is evaluated in PLC channels with measured impulse responses in the presence of measured noise. Computer simulation results show that the bit rate of the OQAM-MCT system is improved using both an adaptive equalizer and noise canceller, and that the OQAM-MCT system achieves better performance than an OFDM system with an insufficient length of the guard interval.</p>]]></description>
<dc:creator><![CDATA[KUNISHIMA, H., KOGA, H., MUTA, O., AKAIWA, Y.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3112</dc:identifier>
<dc:title><![CDATA[Joint Use of Adaptive Equalization and Cyclic Noise Cancellation for Band-Limited OQAM Based Multi-Carrier Transmission in Power-Line Communication Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3120</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3112</prism:startingPage>
<prism:section>Special Section on Wideband Systems -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3121?rss=1">
<title><![CDATA[Construction of Orthogonal Overlapping Pulses for Impulse Radio Communications]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3121?rss=1</link>
<description><![CDATA[<p>A procedure is developed to construct a time-limited pulse for its use in the short-range impulse radio communications. The even-numbered shifts of the pulse constitute a train of overlapping pulses. The pulses are intentionally made orthogonal to the second derivative of one another. This orthogonality makes it possible to detect the received pulses, which are assumed to be the second derivative of the transmitted pulses, by means of correlation with the original pulses. An example pulse is presented that complies with the FCC regulation for indoor ultra-wide bandwidth radio communications.</p>]]></description>
<dc:creator><![CDATA[KAMADA, M., OZLEM, S., HABUCHI, H.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3121</dc:identifier>
<dc:title><![CDATA[Construction of Orthogonal Overlapping Pulses for Impulse Radio Communications]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3129</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3121</prism:startingPage>
<prism:section>Special Section on Wideband Systems -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3130?rss=1">
<title><![CDATA[Interference Detection Based on AIC Using EM Algorithm for UWB MB-OFDM Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3130?rss=1</link>
<description><![CDATA[<p>In this paper, we propose a new algorithm to detect the presence of narrow band interference signals on the band of an Ultra Wide-Band (UWB) system when the UWB spectrum overlaps the bands of other narrow band wireless services. In our proposed algorithm for an UWB Multi-Band Orthogonal Frequency Division Multiplexing (MB-OFDM) system, an appropriate model is selected from the assumed interference models based on the Akaike Information Criterion (AIC) which is an explicit theoretic criterion and a measure of fit of the model. The proposed algorithm does not need a priori information on the interference signals except that we can reduce a computational complexity to implement the algorithm if we have knowledge of the bands of the interference signals. Furthermore, we introduce the Expectation Maximization (EM) algorithm to our algorithm in order to estimate the transmitted signals and the interference signals simultaneously. The proposed algorithm may not require the pilot symbols in the assumed UWB system to detect the presence of other systems. By computer simulations, we show that the proposed algorithm validly detects the presence of interference signals on the UWB band.</p>]]></description>
<dc:creator><![CDATA[FUJII, M., MINAKAWA, A., WATANABE, Y., ITAMI, M., ITOH, K.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3130</dc:identifier>
<dc:title><![CDATA[Interference Detection Based on AIC Using EM Algorithm for UWB MB-OFDM Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3139</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3130</prism:startingPage>
<prism:section>Special Section on Wideband Systems -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3140?rss=1">
<title><![CDATA[Analysis on IR/TR-UWB Interference against Narrowband Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3140?rss=1</link>
<description><![CDATA[<p>This paper presents the analysis of in-band interference caused by pulse-based ultra-wideband (UWB) systems. The analysis contains both plain Impulse Radio UWB (IR-UWB) and Transmitted Reference UWB (TR-UWB) systems as a source of interference. The supposed victim is a narrowband BPSK system with a band-pass filter. The effect of pulse-based UWB systems is analyzed in terms of bit error rate. The analysis is given in terms of the specific combinations of pulse repetition frequency and center frequency of the narrowband bandpass filter. In those situations, the UWB interference cannot be modeled as a Gaussian noise. It also manifests situations in which the victim is under the severest or the slightest interference from TR-UWB. According to its result, the analysis is validated via simulation.</p>]]></description>
<dc:creator><![CDATA[SHIMIZU, Y., SANADA, Y.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3140</dc:identifier>
<dc:title><![CDATA[Analysis on IR/TR-UWB Interference against Narrowband Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3149</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3140</prism:startingPage>
<prism:section>Special Section on Wideband Systems -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3150?rss=1">
<title><![CDATA[Exact Error Rate Analysis for Pulsed DS- and Hybrid DS/TH-CDMA in Nakagami Fading]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3150?rss=1</link>
<description><![CDATA[<p>Exact bit error probabilities (BEP) are derived in closed-form for binary pulsed direct sequence (DS-) and hybrid direct sequence time hopping code division multiple access (DS/TH-CDMA) systems that have potential applications in ultra-wideband (UWB) communications. Flat Nakagami fading channel is considered and the characteristic function (CF) method is adopted. An exact expression of the CF is obtained through a straightforward method, which is simple and good for any arbitrary pulse shape. The CF is then used to obtain the exact BEP that requires less computational complexity than the method based on improved Gaussian approximation (IGA). It is shown under identical operating conditions that the shape of the CF, as well as, the BEP differs considerably for the two systems. While both the systems perform comparably in heavily faded channel, the hybrid system shows better BEP performance in lightly-faded channel. The CF and BEP also strongly depend on chip length and chip-duty that constitute the processing gain (PG). Different combinations of the parameters may result into the same PG and the BEP of a particular system for a constant PG, though remains nearly constant in a highly faded channel, may vary substantially in lightly-faded channel. A comparison of the results from the exact method with those from the standard Gaussian approximation (SGA) reveals that the SGA, though accurate for both the systems in highly-faded channel, becomes extremely optimistic for low-duty systems in lightly-faded channel. The SGA also fails to track several other system trade-offs.</p>]]></description>
<dc:creator><![CDATA[RAHMAN, M. A., SASAKI, S., KIKUCHI, H., HARADA, H., KATO, S.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3150</dc:identifier>
<dc:title><![CDATA[Exact Error Rate Analysis for Pulsed DS- and Hybrid DS/TH-CDMA in Nakagami Fading]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3162</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3150</prism:startingPage>
<prism:section>Special Section on Wideband Systems -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3163?rss=1">
<title><![CDATA[Cyclic Prefix Signaling for Pulse Shape Modulation UWB RAKE Receivers]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3163?rss=1</link>
<description><![CDATA[<p>Combining transmission of ultra wideband pulses, organized in blocks, with the inclusion of cyclic prefixing pulses yields a pulsewidth periodic signal at the receiver. Although unknown, this signal fits perfectly the diversity exploitive architecture of a RAKE receiver. Aiming to profit from this signal arrangement, we propose a pulse shape modulation system employing a RAKE receiver that estimates this periodic signal during a training interval and uses the estimated values for detection of data symbols. Our proposal relies on the invariability of the multipath propagation channel during the transmission of a UWB packet, the adequate application of the cyclic prefix, and the fact that different transmitted pulses result in different periodic signals at the receiver. This system is equivalent to transforming the multipath nature of the UWB propagation channel into a multichannel digital communications affected solely by additive noise. Our proposal is important because it ameliorates the performance of a pulse shape modulation RAKE receiver. On the other hand, the cost of our proposed system resides in the inefficiencies product of the cyclic prefix inclusion.</p>]]></description>
<dc:creator><![CDATA[CARTAGENA GORDILLO, A., KOHNO, R.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3163</dc:identifier>
<dc:title><![CDATA[Cyclic Prefix Signaling for Pulse Shape Modulation UWB RAKE Receivers]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3172</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3163</prism:startingPage>
<prism:section>Special Section on Wideband Systems -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3173?rss=1">
<title><![CDATA[Ultra Wideband Electromagnetic Phantoms for Antennas and Propagation Studies]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3173?rss=1</link>
<description><![CDATA[<p>Ultra wideband (UWB) technologies are expected to be used in ultra-high-speed wireless personal area networks (WPAN) and wireless body area networks (WBAN). UWB human electromagnetic phantoms are useful for performance evaluation of antennas mounted in the vicinity of a human body and channel assessment when a human body blocks a propagation path. Publications on UWB phantoms, however, have been limited so far. This paper describes the development of liquid UWB phantom material (aqueous solution of sucrose) and UWB arm and torso phantoms. The UWB phantoms are not intended to evaluate a specific absorption rate (SAR) in a human body, because UWB devices are supposed to transmit at very low power and thus should pose no human hazard.</p>]]></description>
<dc:creator><![CDATA[YAMAMOTO, H., ZHOU, J., KOBAYASHI, T.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3173</dc:identifier>
<dc:title><![CDATA[Ultra Wideband Electromagnetic Phantoms for Antennas and Propagation Studies]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3182</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3173</prism:startingPage>
<prism:section>Special Section on Wideband Systems -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3183?rss=1">
<title><![CDATA[Performance Evaluation of Human Body Detection Using UWB-IR Indoor Channels]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3183?rss=1</link>
<description><![CDATA[<p>Delay profile of ultra-wideband impulse-radio (UWB-IR) indoor channel fluctuates for a physical change such as intruder. This paper investigates a human body detection using the UWB-IR in order to protect a house, not a room, because the radio with high range resolution can penetrate into the inner walls and also the reflected paths from human body are discriminated in time domain. The usefulness is experimentally investigated under a scenario which someone intrudes into a typical house with four rooms and walks around.</p>]]></description>
<dc:creator><![CDATA[TERASAKA, K., HIGASHIKATSURAGI, K., ONO, K., KAJIWARA, A.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3183</dc:identifier>
<dc:title><![CDATA[Performance Evaluation of Human Body Detection Using UWB-IR Indoor Channels]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3189</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3183</prism:startingPage>
<prism:section>Special Section on Wideband Systems -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3190?rss=1">
<title><![CDATA[Measurement of Ultra Wideband Radar Cross Sections of an Automobile at Ka Band Using Circular Polarizations]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3190?rss=1</link>
<description><![CDATA[<p>Ultra wideband (UWB) radar cross sections (RCSs) of several targets have been measured using various combinations of transmitting and receiving linear polarizations (V-V, H-H, and +45&deg;&ndash;&ndash;45&deg;) with a view to obtaining information on the design of vehicular short-range radars. This paper reports the UWB RCSs ( <SUB>LR</SUB> and <SUB>LL</SUB>) of a typical passenger automobile using two circular polarization combinations (L and R denote left and right circular polarizations). The wideband measurements were carried out with use of a vector network analyzer by sweeping the frequency from 24.5 to 28.8 GHz in a radio anechoic chamber. The UWB RCSs were derived by integrating the received power in the frequency domain. Similar to the linear polarization results, fluctuations of the RCSs were smaller in the UWB than in narrowband for both L-R and L-L, because the ultra-wide bandwidth cancels out RCS plunges caused by narrowband interference among reflected waves from various facets of the target. The median of (<SUB>LR</SUB>&ndash;<SUB>LL</SUB>) was 2 dB, while the median of (<SUB>HH</SUB>&ndash;<SUB>+45&deg;&ndash;&ndash;45&deg;</SUB>) or (<SUB>VV</SUB>&ndash;<SUB>+45&deg;&ndash;&ndash;45&deg;</SUB>) was 6 dB. This is because the body of the automobile comprises a number of smaller scattering objects yielding <SUB>LL</SUB>, either similar to the corner reflectors or asymmetrical to the radar boresight. Frequency-domain responses showed a number of notches caused by the interference between numerous reflecting waves having power levels of a similar order and different round-trip path lengths. Some representative reflective parts of the automobile were identified through analyses of time-domain responses.</p>]]></description>
<dc:creator><![CDATA[OSAKI, H., NISHIDE, T., KOBAYASHI, T.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3190</dc:identifier>
<dc:title><![CDATA[Measurement of Ultra Wideband Radar Cross Sections of an Automobile at Ka Band Using Circular Polarizations]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3196</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3190</prism:startingPage>
<prism:section>Special Section on Wideband Systems -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3197?rss=1">
<title><![CDATA[Selective Signal Combining for Effective BER Improvement in Noncoherent IR-UWB Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3197?rss=1</link>
<description><![CDATA[<p>In order to effectively improve the BER (Bit Error Rate) performance of noncoherent IR-UWB (Impulse Radio Ultra Wide Band) systems utilizing 2PPM (Binary Pulse Position Modulation), we propose a selective signal combining scheme which performs selective combination of received signals by estimating the SNR (Signal-to-Noise Ratio) of the energies during the pulse width interval.</p>]]></description>
<dc:creator><![CDATA[KIM, J., KIM, S., SUNG, W., SHIN, Y.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3197</dc:identifier>
<dc:title><![CDATA[Selective Signal Combining for Effective BER Improvement in Noncoherent IR-UWB Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3200</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3197</prism:startingPage>
<prism:section>Special Section on Wideband Systems -- Letters</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3201?rss=1">
<title><![CDATA[A Study on Possibility of Detecting IEEE802.15.4a Signals for Spectrum Sharing]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3201?rss=1</link>
<description><![CDATA[<p>In March, 2007, IEEE802.15.4a was standardized as a low-rate and low-power UWB system for sensor networks. In general, detection of the IEEE802.15.4a signal is considered to be difficult because of its low transmitting power density and low duty cycle. However, if detecting of the IEEE802.15.4a signal is available, it is possible to avoid interference issues both among the IEEE802.15.4a systems and between the 15.4a and other UWB systems. This letter proposes a simple detection method using non-coherent detectors. The possibility of detecting of the IEEE802.15.4a signal by proposal detection method was examined. By conducting experiments with an emulated 15.4a RF signal, the signal detection probability was examined, and 15.4a signal from the range of about 11 meters in the radius could be detected. From this observation, the CSMA/CA method with detecting the signal in 15.4a system may be applied for alternative access method for 15.4a systems.</p>]]></description>
<dc:creator><![CDATA[HASEGAWA, M., IKEGAMI, T., TAKIZAWA, K.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3201</dc:identifier>
<dc:title><![CDATA[A Study on Possibility of Detecting IEEE802.15.4a Signals for Spectrum Sharing]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3205</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3201</prism:startingPage>
<prism:section>Special Section on Wideband Systems -- Letters</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3206?rss=1">
<title><![CDATA[Special Section on Concurrent/Real-time and Hybrid Systems: Theory and Applications]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3206?rss=1</link>
<description><![CDATA[]]></description>
<dc:creator><![CDATA[Yamane, S.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3206</dc:identifier>
<dc:title><![CDATA[Special Section on Concurrent/Real-time and Hybrid Systems: Theory and Applications]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3206</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3206</prism:startingPage>
<prism:section>Special Section on Concurrent/Real-time and Hybrid Systems: Theory and Applications</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3207?rss=1">
<title><![CDATA[MceSim: A Multi-Car Elevator Simulator]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3207?rss=1</link>
<description><![CDATA[<p>Multi-Car Elevator (MCE) systems, which consist of several independent cars built in the same shaft, are being considered as the elevators of the next generation. In this paper, we present <I>MceSim</I>, a simulator of MCE systems. MceSim is an open source software available to the public, and it can be used as a common testbed to evaluate different control methods related to MCE systems. MceSim was used in the group controller performance competition: CST Solution Competition 2007. This experience has proven MceSim to be a fully functional testbed for MCE systems.</p>]]></description>
<dc:creator><![CDATA[MIYAMOTO, T., YAMAGUCHI, S.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3207</dc:identifier>
<dc:title><![CDATA[MceSim: A Multi-Car Elevator Simulator]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3214</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3207</prism:startingPage>
<prism:section>Special Section on Concurrent/Real-time and Hybrid Systems: Theory and Applications -- Paper</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3215?rss=1">
<title><![CDATA[An Algorithm to Minimize Average Service Completion Time for the Group Controller of Multi-Car Elevator Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3215?rss=1</link>
<description><![CDATA[<p>Recently, multi-car elevator (MCE) system has captured attention as an effective mean for the improvement of transportation capability in a high-rise building. The MCE has two or more cars in one shaft. In this paper, we propose an algorithm for group controllers of MCE system, and show the effectiveness of our algorithm through computer simulation.</p>]]></description>
<dc:creator><![CDATA[KURODA, Y., NAKATA, M.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3215</dc:identifier>
<dc:title><![CDATA[An Algorithm to Minimize Average Service Completion Time for the Group Controller of Multi-Car Elevator Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3218</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3215</prism:startingPage>
<prism:section>Special Section on Concurrent/Real-time and Hybrid Systems: Theory and Applications -- Letter</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3219?rss=1">
<title><![CDATA[Performance Evaluation of Workflows Using Continuous Petri Nets with Interval Firing Speeds]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3219?rss=1</link>
<description><![CDATA[<p>In this paper, we study performance evaluation of workflow-based information systems. Because of state space explosion, analysis by stochastic models, such as stochastic Petri nets and queuing models, is not suitable for workflow systems in which a large number of flow instances run concurrently. We use fluid-flow approximation technique to overcome this difficulty. In the proposed method, GSPN (Generalized Stochastic Petri Nets) models representing workflows are approximated by a class of timed continuous Petri nets, called routing timed continuous Petri nets (RTCPN). In RTCPN models, each discrete set is approximated by a continuous region on a real-valued vector space, and variance in probability distribution is replaced with a real-valued interval. Next we derive piecewise linear systems from RTCPN models, and use interval methods to compute guaranteed enclosures for state variables. As a case study, we solve an optimal resource assignment problem for a paper review process.</p>]]></description>
<dc:creator><![CDATA[HIRAISHI, K.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3219</dc:identifier>
<dc:title><![CDATA[Performance Evaluation of Workflows Using Continuous Petri Nets with Interval Firing Speeds]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3228</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3219</prism:startingPage>
<prism:section>Special Section on Concurrent/Real-time and Hybrid Systems: Theory and Applications -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3229?rss=1">
<title><![CDATA[Routing Autonomous Vehicles in the Improving Initial Task Assignment and Avoiding Deadlock Method]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3229?rss=1</link>
<description><![CDATA[<p>This paper discusses an on-line Tasks Assignment and Routing Problem (TARP) for Autonomous Transportation Systems (ATSs) in manufacturing systems. The TARP is a constrained version of the Pickup and Delivery Problem with Time Windows (PDPTW). In our former study, a cooperative algorithm, called the triple loop method, with autonomous distributed agents has been proposed. The Improving initial Task Assignment and Avoiding Deadlock method (ITAAD) is a faster algorithm than the triple loop method. In this paper, we propose a new vehicle routing method for the ITAAD. Results of computational experiments show effectiveness of the proposed routing method.</p>]]></description>
<dc:creator><![CDATA[MORIHIRO, Y., MIYAMOTO, T., KUMAGAI, S.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3229</dc:identifier>
<dc:title><![CDATA[Routing Autonomous Vehicles in the Improving Initial Task Assignment and Avoiding Deadlock Method]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3236</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3229</prism:startingPage>
<prism:section>Special Section on Concurrent/Real-time and Hybrid Systems: Theory and Applications -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3237?rss=1">
<title><![CDATA[Automatic Generation of User Manuals without Automation Surprises for Human-Machine Systems Modeled by Discrete Event Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3237?rss=1</link>
<description><![CDATA[<p>In human-machine systems, a user gets abstracted information of a machine via an interface and operates it referring to a manual. If a manual has an erroneous description leading to automation surprises, the user may be lost in his/her operations so that he/she may make a serious human error. In this paper, we propose an algorithm for generating a manual by which automation surprises never occur. We model the machine and the interface as a discrete event system and a mapping from machine's state to a display of the interface, respectively. First, we represent a manual as a finite language and model behavior of the system operated by the user with the manual as a tree called an operational tree. Next, we characterize three automation surprises using the tree. Finally, we propose an algorithm for generating an operational tree by which the machine reaches a target state.</p>]]></description>
<dc:creator><![CDATA[USHIO, T., TAKAHASHI, S.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3237</dc:identifier>
<dc:title><![CDATA[Automatic Generation of User Manuals without Automation Surprises for Human-Machine Systems Modeled by Discrete Event Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3244</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3237</prism:startingPage>
<prism:section>Special Section on Concurrent/Real-time and Hybrid Systems: Theory and Applications -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3245?rss=1">
<title><![CDATA[Adaptive Fair Resource Allocation for Energy and QoS Trade-Off Management]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3245?rss=1</link>
<description><![CDATA[<p>In real-time embedded systems, there is requirement for adapting both energy consumption and Quality of Services (QoS) of tasks according to their importance. This paper proposes an adaptive power-aware resource allocation method to resolve a trade-off between the energy consumption and QoS levels according to their importance with guaranteeing fairness. The proposed resource allocator consists of two components: the total resource optimizer to search for the optimal total resource and QoS-fairness-based allocator to allocate resource to tasks guaranteeing the fairness. These components adaptively achieve the optimal resource allocation formulated by a nonlinear optimization problem with the time complexity <I>O(n)</I> for the number of tasks <I>n</I> even if tasks' characteristics cannot be identified precisely. The simulation result shows that the rapidness of the convergence of the resource allocation to the optimal one is suitable for real-time systems with large number of tasks.</p>]]></description>
<dc:creator><![CDATA[HARADA, F., USHIO, T., NAKAMOTO, Y.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3245</dc:identifier>
<dc:title><![CDATA[Adaptive Fair Resource Allocation for Energy and QoS Trade-Off Management]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3252</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3245</prism:startingPage>
<prism:section>Special Section on Concurrent/Real-time and Hybrid Systems: Theory and Applications -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3253?rss=1">
<title><![CDATA[Exact Cost Performance Analysis of Piecewise Affine Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3253?rss=1</link>
<description><![CDATA[<p>A method for the exact cost performance analysis of autonomous discrete-time piecewise affine systems is presented. Cost performance refers to the average trajectory cost over the entire region of attraction of the origin. The trajectory cost is based on the infinite-horizon cost. First, a reverse reachability algorithm which constructs the explicit piecewise quadratic trajectory cost function over the entire region of attraction of the origin is presented. Then, an explicit expression for the integral of a quadratic function over a simplex of arbitrary dimension is derived. Thus, the piecewise quadratic trajectory cost function can be integrated exactly and efficiently in order to determine the cost performance of the system as a whole. This alleviates the need to perform a large number of simulations.</p>]]></description>
<dc:creator><![CDATA[GONDHALEKAR, R., IMURA, J.-i.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3253</dc:identifier>
<dc:title><![CDATA[Exact Cost Performance Analysis of Piecewise Affine Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3260</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3253</prism:startingPage>
<prism:section>Special Section on Concurrent/Real-time and Hybrid Systems: Theory and Applications -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3261?rss=1">
<title><![CDATA[A Formal Approach for Milk-Run Transport Logistics]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3261?rss=1</link>
<description><![CDATA[<p>A formal approach for specifying and reasoning about earth-friendly logistics management systems is presented. To reduce fossil fuel consumption and carbon dioxide emissions resulting from transport, we must enhance the transport efficiency of trucks, which play an essential role as carriers in modern logistics services. This paper addresses the milk-run approach. It is one of the most effective and popular solutions to this problem, but it makes it be complicated to implement in a logistics management system. We propose a language for specifying the routes of trucks and an order relation between the requirements of routes and the possible routes of trucks. The former is formulated as process calculus and the latter selects suitable trucks according to their routes.</p>]]></description>
<dc:creator><![CDATA[SATOH, I.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3261</dc:identifier>
<dc:title><![CDATA[A Formal Approach for Milk-Run Transport Logistics]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3268</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3261</prism:startingPage>
<prism:section>Special Section on Concurrent/Real-time and Hybrid Systems: Theory and Applications -- Papers</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3269?rss=1">
<title><![CDATA[Stepwise Phase Difference Restoration Method for DOA Estimation of Multiple Sources]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3269?rss=1</link>
<description><![CDATA[<p>We propose a new methodology of DOA (direction of arrival) estimation named <b>SPIRE</b> (Stepwise Phase dIfference REstoration) that is able to estimate sound source directions even if there is more than one source in a reverberant environment. DOA estimation in reverberant environments is difficult because the variance of the direction of an estimated sound source increases in reverberant environments. Therefore, we want the distance between microphones to be long. However, because of the spatial aliasing problem, the distance cannot be longer than half the wavelength of the maximum frequency of a source. DOA estimation performance of SPIRE is not limited by the spatial aliasing problem. The major feature of SPIRE is restoration of the phase difference of a microphone pair (M1) by using the phase difference of another microphone pair (M2) under the condition that the distance between the M1 microphones is longer than the distance between the M2 microphones. This restoration process enables the reduction of the variance of an estimated sound source direction and can alleviates the spatial aliasing problem that occurs with the M1 phase difference using direction estimation of the M2 microphones. The experimental results in a reverberant environment (reverberation time = about 300 ms) indicate that even when there are multiple sources, the proposed method can estimate the source direction more accurately than conventional methods. In addition, DOA estimation performance of SPIRE with the array length 0.2 m is shown to be almost equivalent to that of GCC-PHAT with the array length 0.5 m. SPIRE can executes DOA estimation with a smaller microphone array than GCC-PHAT. From the viewpoint of the hardware size and coherence problem, the array length is required to be as small as possible. This feature of SPIRE is preferable.</p>]]></description>
<dc:creator><![CDATA[TOGAMI, M., OBUCHI, Y.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3269</dc:identifier>
<dc:title><![CDATA[Stepwise Phase Difference Restoration Method for DOA Estimation of Multiple Sources]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3281</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3269</prism:startingPage>
<prism:section>Regular Section -- Papers -- Engineering Acoustics</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3282?rss=1">
<title><![CDATA[Low Power Realization and Synthesis of Higher-Order FIR Filters Using an Improved Common Subexpression Elimination Method]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3282?rss=1</link>
<description><![CDATA[<p>The complexity of Finite Impulse Response (FIR) filters is mainly dominated by the number of adders (subtractors) used to implement the coefficient multipliers. It is well known that Common Subexpression Elimination (CSE) method based on Canonic Signed Digit (CSD) representation considerably reduces the number of adders in coefficient multipliers. Recently, a binary-based CSE (BSE) technique was proposed, which produced better reduction of adders compared to the CSD-based CSE. In this paper, we propose a new 4-bit binary representation-based CSE (BCSE-4) method which employs 4-bit Common Subexpressions (CSs) for implementing higher order low-power FIR filters. The proposed BCSE-4 offers better reduction of adders by eliminating the redundant 4-bit CSs that exist in the binary representation of filter coefficients. The reduction of adders is achieved with a small increase in critical path length of filter coefficient multipliers. Design examples show that our BCSE-4 gives an average power consumption reduction of 5.2% and 6.1% over the best known CSE method (BSE, NR-SCSE) respectively, when synthesized with TSMC-0.18 &micro;m technology. We show that our BCSE-4 offers an overall adder reduction of 6.5% compared to BSE without any increase in critical path length of filter coefficient multipliers.</p>]]></description>
<dc:creator><![CDATA[SMITHA, K.G., VINOD, A.P.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3282</dc:identifier>
<dc:title><![CDATA[Low Power Realization and Synthesis of Higher-Order FIR Filters Using an Improved Common Subexpression Elimination Method]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3292</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3282</prism:startingPage>
<prism:section>Regular Section -- Papers -- Digital Signal Processing</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3293?rss=1">
<title><![CDATA[Suppression of Limit Cycles in Servo Systems Using Gain Limit Compensator]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3293?rss=1</link>
<description><![CDATA[<p>In high-precision positioning systems, the limit cycles induced by friction effects result in a significant reduction in the positioning performance; particularly when the servo system utilizes a high gain controller. Accordingly, the current study presents a compensation scheme consisting of a dead-zone function and an integral term to limit the equivalent gain of unspecified controllers to the stable range. The proposed compensation scheme not only ensures that the feedback loop system remains stable, but also provides a simple and effective mechanism for preventing the users from inadvertently setting control gains which degrade the positioning performance of the system. The simulation results confirm the ability of the gain limit compensation scheme to suppress the effects of limit cycles and therefore demonstrate its feasibility for practical applications.</p>]]></description>
<dc:creator><![CDATA[LIAO, C.-H., CHOU, F.-C., TUNG, P.-C., CHEN, Y.-D.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3293</dc:identifier>
<dc:title><![CDATA[Suppression of Limit Cycles in Servo Systems Using Gain Limit Compensator]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3296</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3293</prism:startingPage>
<prism:section>Regular Section -- Papers -- Systems and Control</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3297?rss=1">
<title><![CDATA[Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3297?rss=1</link>
<description><![CDATA[<p>This paper proposes a novel hybrid NoC structure and a dynamic job distribution algorithm which can reduce system area and power consumption by reducing packet drop rate for various multimedia applications. The proposed NoC adopts different network structures between sub-clusters. Network structure is determined by profiling application program so that packet drop rate can be minimized. The proposed job distribution algorithm assigns every job to the sub-cluster where packet drop rate can be minimized for each multimedia application program. The proposed scheme targets multimedia applications frequently used in modern embedded systems, such as MPEG4 and MP3 decoders, GPS positioning systems, and OFDM demodulators. Experimental results show that packet drop rate was reduced by 31.6% on the average, when compared to complex network structure topologies consisting of sub-clusters of same topology. Chip area and power consumption were reduced by 16.0% and 34.0%, respectively.</p>]]></description>
<dc:creator><![CDATA[KIM, W. J., HWANG, S. Y.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3297</dc:identifier>
<dc:title><![CDATA[Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3303</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3297</prism:startingPage>
<prism:section>Regular Section -- Papers -- VLSI Design Technology and CAD</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3304?rss=1">
<title><![CDATA[Extracting Communities from Complex Networks by the k-Dense Method]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3304?rss=1</link>
<description><![CDATA[<p>To understand the structural and functional properties of large-scale complex networks, it is crucial to efficiently extract a set of cohesive subnetworks as communities. There have been proposed several such community extraction methods in the literature, including the classical <I>k</I>-core decomposition method and, more recently, the <I>k</I>-clique based community extraction method. The <I>k</I>-core method, although computationally efficient, is often not powerful enough for uncovering a detailed community structure and it produces only coarse-grained and loosely connected communities. The <I>k</I>-clique method, on the other hand, can extract fine-grained and tightly connected communities but requires a substantial amount of computational load for large-scale complex networks. In this paper, we present a new notion of a subnetwork called <I>k</I>-dense, and propose an efficient algorithm for extracting <I>k</I>-dense communities. We applied our method to the three different types of networks assembled from real data, namely, from blog trackbacks, word associations and Wikipedia references, and demonstrated that the <I>k</I>-dense method could extract communities almost as efficiently as the <I>k</I>-core method, while the qualities of the extracted communities are comparable to those obtained by the <I>k</I>-clique method.</p>]]></description>
<dc:creator><![CDATA[SAITO, K., YAMADA, T., KAZAMA, K.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3304</dc:identifier>
<dc:title><![CDATA[Extracting Communities from Complex Networks by the k-Dense Method]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3311</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3304</prism:startingPage>
<prism:section>Regular Section -- Papers -- Graphs and Networks</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3312?rss=1">
<title><![CDATA[A Secure Construction for Threshold Anonymous Password-Authenticated Key Exchange]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3312?rss=1</link>
<description><![CDATA[<p>At Indocrypt 2005, Viet et al., [21] have proposed an anonymous password-authenticated key exchange (PAKE) protocol and its threshold construction both of which are designed for client's password-based authentication and anonymity against a passive server, who does not deviate the protocol. In this paper, we first point out that their threshold construction is completely insecure against off-line dictionary attacks. For the threshold <I>t</I> &gt; 1, we propose a secure threshold anonymous PAKE (for short, TAP) protocol with the number of clients <I>n</I> upper-bounded, such that <I>n</I> &le; 2 N &ndash; 1 &ndash; 1, where <I>N</I> is a dictionary size of passwords. We rigorously prove that the TAP protocol has semantic security of session keys in the random oracle model by showing the reduction to the computational Diffie-Hellman problem. In addition, the TAP protocol provides unconditional anonymity against a passive server. For the threshold <I>t</I> = 1, we propose an efficient anonymous PAKE protocol that significantly improves efficiency in terms of computation costs and communication bandwidth compared to the original (not threshold) anonymous PAKE protocol [21].</p>]]></description>
<dc:creator><![CDATA[SHIN, S., KOBARA, K., IMAI, H.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3312</dc:identifier>
<dc:title><![CDATA[A Secure Construction for Threshold Anonymous Password-Authenticated Key Exchange]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3324</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3312</prism:startingPage>
<prism:section>Regular Section -- Papers -- Cryptography and Information Security</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3325?rss=1">
<title><![CDATA[Inefficacious Conditions of the Frobenius Primality Test and Grantham's Problem]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3325?rss=1</link>
<description><![CDATA[<p>For determining whether an input number is prime, there are two kinds of algorithms, a <I>primality test</I> and a <I>primality proving</I>. A <I>primality test</I> is very efficient but probabilistic, that is, there are certain errors in determining primality. On the other hand, a <I>primality proving</I> always gives a correct answer but it is not so efficient. Grantham proposed a very interesting problem on the Quadratic Frobenius Test (<I>QFT</I>) which is a <I>primality test</I>. If we negatively solve the problem, then we can construct a <I>primality proving</I> more efficient than any other existing <I>primality proving</I>. To solve Grantham's problem, it is important to study when <I>QFT</I> fails. In this paper, as the first step to solve Grantham's problem, we show two conditions on a given odd composite number <I>n</I> and parameters <I>a,b</I> of <I>QFT</I> such that <I>n</I> passes <I>QFT</I> for <I>a,b</I>. Based on these conditions, we made a computational experiment that may suggest the problem will be negatively solved. Moreover, the two conditions give two algorithms computing a pair <I>(a,b)</I> for which a given odd composite number <I>n</I> passes <I>QFT</I>, where <I>n</I>'s prime factorization is known.</p>]]></description>
<dc:creator><![CDATA[SHINOHARA, N.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3325</dc:identifier>
<dc:title><![CDATA[Inefficacious Conditions of the Frobenius Primality Test and Grantham's Problem]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3334</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3325</prism:startingPage>
<prism:section>Regular Section -- Papers -- Cryptography and Information Security</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3335?rss=1">
<title><![CDATA[Interference Cancellation Technique Based on Discovery of Spreading Codes of Interference Signals and Maximum Correlation Detection for DS-CDMA System]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3335?rss=1</link>
<description><![CDATA[<p>This paper presents a novel interference cancellation (IC) scheme for both synchronous and asynchronous direct-sequence code-division multiple-access (DS-CDMA) wireless channels. In the DS-CDMA system, the multiple access interference (MAI) and the near-far problem (NFP) are the two factors which reduce the capacity of the system. In this paper, we propose a new algorithm that is able to detect all interference signals as an individual MAI signal by maximum correlation detection. It is based on the discovery of all the unknowing spreading codes of the interference signals. Then, all possible MAI patterns so called replicas are generated as a summation of interference signals. And the true MAI pattern is found by taking correlation between the received signal and the replicas. Moreover, the receiver executes MAI cancellation in a successive manner, removing all interference signals by single-stage. Numerical results will show that the proposed IC strategy, which alleviates the detrimental effect of the MAI and the near-far problem, can significantly improve the system performance. Especially, we can obtain almost the same receiving characteristics as in the absense of interference for asynchrnous system when received powers are equal. Also, the same performances can be seen under any received power state for synchronous system.</p>]]></description>
<dc:creator><![CDATA[HETTIARACHCHI, R., YOKOYAMA, M., UEHARA, H.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3335</dc:identifier>
<dc:title><![CDATA[Interference Cancellation Technique Based on Discovery of Spreading Codes of Interference Signals and Maximum Correlation Detection for DS-CDMA System]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3345</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3335</prism:startingPage>
<prism:section>Regular Section -- Papers -- Spread Spectrum Technologies and Applications</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3346?rss=1">
<title><![CDATA[Real-Time Road Sign Detection Using Fuzzy-Boosting]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3346?rss=1</link>
<description><![CDATA[<p>This paper describes a vision-based and real-time system for detecting road signs from within a moving vehicle. The system architecture which is proposed in this paper consists of two parts, the learning and the detection part of road sign images. The proposed system has the standard architecture with adaboost algorithm. Adaboost is a popular algorithm which used to detect an object in real time. To improve the detection rate of adaboost algorithm, this paper proposes a new combination method of classifiers in every stage. In the case of detecting road signs in real environment, it can be ambiguous to decide to which class input images belong. To overcome this problem, we propose a method that applies fuzzy measure and fuzzy integral which use the importance and the evaluated values of classifiers within one stage. It is called fuzzy-boosting in this paper. Also, to improve the speed of a road sign detection algorithm using adaboost at the detection step, we propose a method which chooses several candidates by using MC generator. In this paper, as the sub-windows of chosen candidates pass classifiers which are made from fuzzy-boosting, we decide whether a road sign is detected or not. Using experiment result, we analyze and compare the detection speed and the classification error rate of the proposed algorithm applied to various environment and condition.</p>]]></description>
<dc:creator><![CDATA[YOON, C., LEE, H., KIM, E., PARK, M.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3346</dc:identifier>
<dc:title><![CDATA[Real-Time Road Sign Detection Using Fuzzy-Boosting]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3355</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3346</prism:startingPage>
<prism:section>Regular Section -- Papers -- Intelligent Transport System</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3356?rss=1">
<title><![CDATA[Lossless-by-Lossy Coding for Scalable Lossless Image Compression]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3356?rss=1</link>
<description><![CDATA[<p>This paper presents a method of scalable lossless image compression by means of lossy coding. A progressive decoding capability and a full decoding for the lossless rendition are equipped with the losslessly encoded bit stream. Embedded coding is applied to large-amplitude coefficients in a wavelet transform domain. The other wavelet coefficients are encoded by a context-based entropy coding. The proposed method slightly outperforms JPEG-LS in lossless compression. Its rate-distortion performance with respect to progressive decoding is close to that of JPEG2000. The spatial scalability with respect to resolution is also available.</p>]]></description>
<dc:creator><![CDATA[SHINODA, K., KIKUCHI, H., MURAMATSU, S.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3356</dc:identifier>
<dc:title><![CDATA[Lossless-by-Lossy Coding for Scalable Lossless Image Compression]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3364</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3356</prism:startingPage>
<prism:section>Regular Section -- Papers -- Image</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3365?rss=1">
<title><![CDATA[Sampled-Data Event Control of Hybrid Systems for Control Specifications Given by Predicate]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3365?rss=1</link>
<description><![CDATA[<p>We consider a hybrid system controlled by a sampled-data controller whose action is periodically time-driven, that is, the control inputs can change only at the particular time instants. Then, we introduce transition systems as semantics of the controlled hybrid systems and consider a control specification given by a predicate. First, we derive a necessary and sufficient condition for the predicate to be control-invariant. Next, we show that there always exists the supremal control-invariant subpredicate for any predicate. Finally, we propose a procedure to compute it and obtain a sampled-data event controller which satisfies it.</p>]]></description>
<dc:creator><![CDATA[TSUCHIE, Y., USHIO, T.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3365</dc:identifier>
<dc:title><![CDATA[Sampled-Data Event Control of Hybrid Systems for Control Specifications Given by Predicate]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3373</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3365</prism:startingPage>
<prism:section>Regular Section -- Papers -- Concurrent Systems</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3374?rss=1">
<title><![CDATA[Fast Tracking of a Real Sinusoid with Multiple Forgetting Factors]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3374?rss=1</link>
<description><![CDATA[<p>In this paper, a recursive Gauss-Newton (RGN) algorithm is first developed for adaptive tracking of the amplitude, frequency and phase of a real sinusoid signal in additive white noise. The derived algorithm is then simplified for computational complexity reduction as well as improved with the use of multiple forgetting factor (MFF) technique to provide a flexible way of keeping track of the parameters with different rates. The effectiveness of the simplified MFF-RGN scheme in sinusoidal parameter tracking is demonstrated via computer simulations.</p>]]></description>
<dc:creator><![CDATA[AMIN, Md. T., LUI, K. W.-K., SO, H.-C.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3374</dc:identifier>
<dc:title><![CDATA[Fast Tracking of a Real Sinusoid with Multiple Forgetting Factors]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3379</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3374</prism:startingPage>
<prism:section>Regular Section -- Letters -- Digital Signal Processing</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3380?rss=1">
<title><![CDATA[n-Mode Singular Vector Selection in Higher-Order Singular Value Decomposition]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3380?rss=1</link>
<description><![CDATA[<p>In this paper, we propose a method for selecting <I>n</I>-mode singular vectors in higher-order singular value decomposition. We select the minimum number of <I>n</I>-mode singular vectors, when the upper bound of a least-squares cost function is thresholded. The reduced <I>n</I>-ranks of all modes of a given tensor are determined automatically and the tensor is represented with the minimum number of dimensions. We apply the selection method to simultaneous low rank approximation of matrices. Experimental results show the effectiveness of the <I>n</I>-mode singular vector selection method.</p>]]></description>
<dc:creator><![CDATA[INOUE, K., URAHAMA, K.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3380</dc:identifier>
<dc:title><![CDATA[n-Mode Singular Vector Selection in Higher-Order Singular Value Decomposition]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3384</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3380</prism:startingPage>
<prism:section>Regular Section -- Letters -- Digital Signal Processing</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3385?rss=1">
<title><![CDATA[Design of CMOS OTAs for Low-Voltage and Low-Power Application]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3385?rss=1</link>
<description><![CDATA[<p>In this letter, two OTAs with MOSFETs operating in the weak inversion region are proposed. One of the OTAs uses the exponential-logarithm transformation algorithm. Furthermore, the other realizes the high-linearity characteristics due to a small fluctuation of the common-terminal voltage of differential pair. The performance of the proposed OTAs was confirmed by HSPICE simulation.</p>]]></description>
<dc:creator><![CDATA[TANAKA, H., TANNO, K., TAMURA, H., MURAO, K.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3385</dc:identifier>
<dc:title><![CDATA[Design of CMOS OTAs for Low-Voltage and Low-Power Application]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3388</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3385</prism:startingPage>
<prism:section>Regular Section -- Letters -- Analog Signal Processing</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3389?rss=1">
<title><![CDATA[Robust Detection Algorithm for Spread Spectrum Audio Watermarking]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3389?rss=1</link>
<description><![CDATA[<p>In this letter we propose a robust detection algorithm for audio watermarking for copyright protection. The watermark is embedded in the time domain of an audio signal by the normally used spread spectrum technique. The scheme of detection is an improvement of the conventional correlation detector. A high-pass filter is applied along with the linear prediction error filter for whitening the audio signal and an adaptive threshold is chosen for decision comparing. Experimental results show that our detection algorithm outperforms the conventional one not only because it improves the robustness to normal attacks but also because it can provide the robustness to time-invariant pitch-scale modification.</p>]]></description>
<dc:creator><![CDATA[LI, L., FANG, X.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3389</dc:identifier>
<dc:title><![CDATA[Robust Detection Algorithm for Spread Spectrum Audio Watermarking]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3392</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3389</prism:startingPage>
<prism:section>Regular Section -- Letters -- Cryptography and Information Security</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3393?rss=1">
<title><![CDATA[High-Rate Space-Time Block Coding Schemes]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3393?rss=1</link>
<description><![CDATA[<p>A rate-6/4 full-diversity orthogonal space-time block code (STBC) is constructed for QPSK and 2 transmit antennas by applying constellation scaling and rotation to the set of quaternions used in Alamouti code. Also given is a rate-9/8 full-diversity quasi-orthogonal space-time block code (QOSTBC) for 4 transmit antennas. Lastly, a rate-10/8 code is presented for 4 transmit antennas. Simulation results indicate that these high-rate codes achieve better throughputs in the high signal-to-noise ratio region.</p>]]></description>
<dc:creator><![CDATA[NGUYEN, D. H. N., NGUYEN, H. H., HOANG, T. D.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3393</dc:identifier>
<dc:title><![CDATA[High-Rate Space-Time Block Coding Schemes]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3397</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3393</prism:startingPage>
<prism:section>Regular Section -- Letters -- Coding Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3398?rss=1">
<title><![CDATA[Subspace Selection for Quadratic Detector of Random Signals in Unknown Correlated Clutter]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3398?rss=1</link>
<description><![CDATA[<p>The Letter deals with constant false alarm rate (CFAR) detection of random Gaussian target signals embedded in Gaussian clutter with unknown covariance. The proposed detector is analyzed on the assumption that clutter covariance is not known and a random target signal has low-rank property. The low-dimensional subspace-based approach leads to a robust false alarm rate (RFAR) detector. The detection performance loss and the false alarm stability loss to unknown clutter covariance have been evaluated for example scenario.</p>]]></description>
<dc:creator><![CDATA[GOLIKOV, V., LEBEDEVA, O.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3398</dc:identifier>
<dc:title><![CDATA[Subspace Selection for Quadratic Detector of Random Signals in Unknown Correlated Clutter]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3402</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3398</prism:startingPage>
<prism:section>Regular Section -- Letters -- Communication Theory and Signals</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3403?rss=1">
<title><![CDATA[Outage Probability of Dual-Hop Amplify-and-Forward Relaying Systems over Shadowed Nakagami-m Fading Channels]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3403?rss=1</link>
<description><![CDATA[<p>This paper studies a dual-hop amplify-and-forward (AF) relaying systems over shadowed Nakagami-<I>m</I> fading channels and derives an approximate analytical expression for the outage probability. The numerical results show that the derived analytical expression can provide very well approximations to the simulation results.</p>]]></description>
<dc:creator><![CDATA[LI, W., WANG, J.-B., CHEN, M.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3403</dc:identifier>
<dc:title><![CDATA[Outage Probability of Dual-Hop Amplify-and-Forward Relaying Systems over Shadowed Nakagami-m Fading Channels]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3405</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3403</prism:startingPage>
<prism:section>Regular Section -- Letters -- Communication Theory and Signals</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3406?rss=1">
<title><![CDATA[New Families of Binary Low Correlation Zone Sequences Based on Interleaved Quadratic Form Sequences]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/11/3406?rss=1</link>
<description><![CDATA[<p>In this letter, new families of binary low correlation zone (LCZ) sequences based on the interleaving technique and quadratic form sequences are constructed, which include the binary LCZ sequence set derived from Gordon-Mills-Welch (GMW) sequences. The constructed sequences have the property that, in a specified zone, the out-of-phase autocorrelation and cross-correlation values are all equal to &ndash;1. Due to this property, such sequences are suitable for quasi-synchronous code-division multiple access (QS-CDMA) systems.</p>]]></description>
<dc:creator><![CDATA[ZHOU, Z., TANG, X.]]></dc:creator>
<dc:date>2008-11-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.11.3406</dc:identifier>
<dc:title><![CDATA[New Families of Binary Low Correlation Zone Sequences Based on Interleaved Quadratic Form Sequences]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>11</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3409</prism:endingPage>
<prism:publicationDate>2008-11-01</prism:publicationDate>
<prism:startingPage>3406</prism:startingPage>
<prism:section>Regular Section -- Letters -- Spread Spectrum Technologies and Applications</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2695?rss=1">
<title><![CDATA[Special Section on Information Theory and Its Applications]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2695?rss=1</link>
<description><![CDATA[]]></description>
<dc:creator><![CDATA[Tokiwa, K.-i.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2695</dc:identifier>
<dc:title><![CDATA[Special Section on Information Theory and Its Applications]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2695</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2695</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2696?rss=1">
<title><![CDATA[Towards Efficient Detection of Two-Dimensional Intersymbol Interference Channels]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2696?rss=1</link>
<description><![CDATA[<p>This paper gives a survey and comparison of algorithms for the detection of binary data in the presence of two-dimensional (2-D) intersymbol interference. This is a general problem of communication theory, because it can be applied to various practical problems in data storage and transmission. Major results on trellis-based detection algorithms, previously disparate are drawn together, and placed into a common framework. All algorithms have better complexity than optimal detection, and complexity is compared. On the one hand, many algorithms perform within 1.0 dB or better of optimal performance. On the other hand, none of these proposed algorithms can find the optimal solution at high SNR, which is surprising. Extensive discussion outlines further open problems.</p>]]></description>
<dc:creator><![CDATA[KURKOSKI, B. M.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2696</dc:identifier>
<dc:title><![CDATA[Towards Efficient Detection of Two-Dimensional Intersymbol Interference Channels]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2703</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2696</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Survey Paper -- Communication Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2704?rss=1">
<title><![CDATA[Large Deviation Theorems Revisited: Information-Spectrum Approach]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2704?rss=1</link>
<description><![CDATA[<p>In this paper we show some new look at large deviation theorems from the viewpoint of the information-spectrum (IS) methods, which has been first exploited in information theory, and also demonstrate a new basic formula for the large deviation rate function in general, which is expressed as a pair of the lower and upper IS rate functions. In particular, we are interested in establishing the general large deviation rate functions that are derivable as the Fenchel-Legendre transform of the cumulant generating function. The final goal is to show, under some mild condition, a necessary and sufficient condition for the IS rate function to be derivable as the Fenchel-Legendre transform of the cumulant generating function, i.e., to be a rate function of G&auml;rtner-Ellis type.</p>]]></description>
<dc:creator><![CDATA[HAN, T.-S.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2704</dc:identifier>
<dc:title><![CDATA[Large Deviation Theorems Revisited: Information-Spectrum Approach]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2719</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2704</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Information Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2720?rss=1">
<title><![CDATA[Strongly Secure Linear Network Coding]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2720?rss=1</link>
<description><![CDATA[<p>In a network with capacity <I>h</I> for multicast, information <I>X<sup>h</sup></I> = (<I>X</I><SUB>1</SUB>, <I>X</I><SUB>2</SUB>, ..., <I>X</I><SUB>h</SUB>) can be transmitted from a source node to sink nodes without error by a linear network code. Furthermore, secret information <I>S<sup>r</sup></I> = (<I>S</I><SUB>1</SUB>, <I>S</I><SUB>2</SUB>, ..., <I>S<SUB>r</SUB></I>) can be transmitted securely against wiretappers by <I>k</I>-secure network coding for <I>k</I> &le; <I>h&ndash;r</I>. In this case, no information of the secret leaks out even if an adversary wiretaps <I>k</I> edges, i.e. channels. However, if an adversary wiretaps <I>k</I> + 1 edges, some <I>S<SUB>i</SUB></I> may leak out explicitly. In this paper, we propose strongly <I>k</I>-secure network coding based on strongly secure ramp secret sharing schemes. In this coding, no information leaks out for every (<I>S<SUB>i<SUB>1</SUB></SUB></I>, <I>S<SUB>i<SUB>2</SUB></SUB></I>, ..., <I>S<SUB>i<SUB>r&ndash;j</SUB></SUB></I>) even if an adversary wiretaps <I>k &plusmn; j</I> channels. We also give an algorithm to construct a strongly <I>k</I>-secure network code directly and a transform to convert a nonsecure network code to a strongly <I>k</I>-secure network code. Furthermore, some sufficient conditions of alphabet size to realize the strongly <I>k</I>-secure network coding are derived for the case of <I>k &lt; h&ndash;r</I>.</p>]]></description>
<dc:creator><![CDATA[HARADA, K., YAMAMOTO, H.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2720</dc:identifier>
<dc:title><![CDATA[Strongly Secure Linear Network Coding]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2728</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2720</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Information Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2729?rss=1">
<title><![CDATA[Sum-Product Decoding of BCH Codes]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2729?rss=1</link>
<description><![CDATA[<p>This paper proposes methods to improve soft-input and soft-output decoding performance of BCH codes by sum-product algorithm (SPA). A method to remove cycles of length four (RmFC) in the Tanner graph has been proposed. However, the RmFC can not realize good decoding performance for BCH codes which have more than one error correcting capability. To overcome this problem, this paper proposes two methods. One is to use a parity check matrix of the echelon canonical form as the starting check matrix of RmFC. The other is to use a parity check matrix that is concatenation (ConC) of multiple parity check matrices. For BCH(31,11,11) code, SPA with ConC realizes Eb/No 3.7 dB better at bit error rate 10<sup>&ndash;5</sup> than the original SPA, and 3.1 dB better than the SPA with only RmFC.</p>]]></description>
<dc:creator><![CDATA[OGIWARA, H., SHIMAMURA, K., SHOHON, T.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2729</dc:identifier>
<dc:title><![CDATA[Sum-Product Decoding of BCH Codes]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2736</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2729</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Coding Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2737?rss=1">
<title><![CDATA[Detailed Evolution of Degree Distributions in Residual Graphs with Joint Degree Distributions]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2737?rss=1</link>
<description><![CDATA[<p>Luby et al. derived evolution of degree distributions in residual graphs for irregular LDPC code ensembles. Evolution of degree distributions in residual graphs is important characteristic which is used for finite-length analysis of the expected block and bit error probability over the binary erasure channel. In this paper, we derive detailed evolution of degree distributions in residual graphs for irregular LDPC code ensembles with joint degree distributions.</p>]]></description>
<dc:creator><![CDATA[NOZAKI, T., KASAI, K., SHIBUYA, T., SAKANIWA, K.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2737</dc:identifier>
<dc:title><![CDATA[Detailed Evolution of Degree Distributions in Residual Graphs with Joint Degree Distributions]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2744</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2737</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Coding Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2745?rss=1">
<title><![CDATA[A Method for Grouping Symbol Nodes of Group Shuffled BP Decoding Algorithm]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2745?rss=1</link>
<description><![CDATA[<p>In this paper, we propose a method for enhancing performance of a sequential version of the belief-propagation (BP) decoding algorithm, the group shuffled BP decoding algorithm for low-density parity-check (LDPC) codes. An improved BP decoding algorithm, called the shuffled BP decoding algorithm, decodes each symbol node in serial at each iteration. To reduce the decoding delay of the shuffled BP decoding algorithm, the group shuffled BP decoding algorithm divides all symbol nodes into several groups. In contrast to the original group shuffled BP, which automatically generates groups according to symbol positions, in this paper we propose a method for grouping symbol nodes which generates groups according to the structure of a Tanner graph of the codes. The proposed method can accelerate the convergence of the group shuffled BP algorithm and obtain a lower error rate in a small number of iterations. We show by simulation results that the decoding performance of the proposed method is improved compared with those of the shuffled BP decoding algorithm and the group shuffled BP decoding algorithm.</p>]]></description>
<dc:creator><![CDATA[SATO, Y., HOSOYA, G., YAGI, H., HIRASAWA, S.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2745</dc:identifier>
<dc:title><![CDATA[A Method for Grouping Symbol Nodes of Group Shuffled BP Decoding Algorithm]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2753</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2745</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Coding Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2754?rss=1">
<title><![CDATA[Density Evolution Analysis of Robustness for LDPC Codes over the Gilbert-Elliott Channel]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2754?rss=1</link>
<description><![CDATA[<p>In this paper, we analyze the robustness for low-density parity-check (LDPC) codes over the Gilbert-Elliott (GE) channel. For this purpose we propose a density evolution method for the case where LDPC decoder uses the mismatched parameters for the GE channel. Using this method, we derive the region of tuples of true parameters and mismatched decoding parameters for the GE channel, where the decoding error probability approaches asymptotically to zero.</p>]]></description>
<dc:creator><![CDATA[KOBAYASHI, M., YAGI, H., MATSUSHIMA, T., HIRASAWA, S.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2754</dc:identifier>
<dc:title><![CDATA[Density Evolution Analysis of Robustness for LDPC Codes over the Gilbert-Elliott Channel]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2764</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2754</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Coding Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2765?rss=1">
<title><![CDATA[A Combined Matrix Ensemble of Low-Density Parity-Check Codes for Correcting a Solid Burst Erasure]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2765?rss=1</link>
<description><![CDATA[<p>A new ensemble of low-density parity-check (LDPC) codes for correcting a solid burst erasure is proposed. This ensemble is an instance of a combined matrix ensemble obtained by concatenating some LDPC matrices. We derive a new bound on the critical minimum span ratio of stopping sets for the proposed code ensemble by modifying the bound for ordinary code ensemble. By calculating this bound, we show that the critical minimum span ratio of stopping sets for the proposed code ensemble is better than that of the conventional one with keeping the same critical exponent of stopping ratio for both ensemble. Furthermore from experimental results, we show that the average minimum span of stopping sets for a solid burst erasure of the proposed codes is larger than that of the conventional ones.</p>]]></description>
<dc:creator><![CDATA[HOSOYA, G., MATSUSHIMA, T., HIRASAWA, S.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2765</dc:identifier>
<dc:title><![CDATA[A Combined Matrix Ensemble of Low-Density Parity-Check Codes for Correcting a Solid Burst Erasure]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2778</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2765</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Coding Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2779?rss=1">
<title><![CDATA[Nonorthogonal CSK/CDMA with Received-Power Adaptive Access Control Scheme]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2779?rss=1</link>
<description><![CDATA[<p>The measurements for Multiple Access Interference (MAI) problems and the improvement of the data rate are key issues on the advanced wireless networks. In this paper, the nonorthogonal Code Shift Keying Code Division Multiple Access (CSK/CDMA) with received-power adaptive access control scheme is proposed. In our system, a user who is ready to send measures the received power from other users, and then the user decides whether to transmit or refrain from transmission according to the received power and a pre-decided threshold. Not only overcoming the MAI problems, but our system also improve the throughput performance. The throughput performance of the proposed system is evaluated by theoretical analysis. Consequently, the nonorthogonal CSK/CDMA system improves by applying received-power adaptive access control. It was also found that the throughput performance of the nonorthogonal CSK/CDMA system is better than that of the orthogonal CSK/CDMA system at any <I>E<SUB>b</SUB>/N<SUB>0</SUB></I>. We conclude that the nonorthogonal CSK/CDMA system with received-power adaptive access control scheme is expected to be effective in advanced wireless networks.</p>]]></description>
<dc:creator><![CDATA[KOMURO, N., HABUCHI, H., TSUBOI, T.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2779</dc:identifier>
<dc:title><![CDATA[Nonorthogonal CSK/CDMA with Received-Power Adaptive Access Control Scheme]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2786</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2779</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Communication Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2787?rss=1">
<title><![CDATA[Soft Decision Directed Channel Estimation with Interference Cancellation for a MIMO System Using Iterative Equalization and Decoding]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2787?rss=1</link>
<description><![CDATA[<p>This paper proposes a novel channel estimation method for iterative equalization in MIMO systems. The proposed method incorporates co-channel interference (CCI) cancellation in the channel estimator and the channel estimation is successively performed with respect to each stream. Accuracy of channel estimation holds the key to be successfully converged the iterative equalization and decoding process. Although the channel estimates can be re-estimated by means of LS (Least Square) channel estimation using tentative decisions obtained in the iterative process, its performance is severely limited in a MIMO system because of erroneous decisions and ill-conditioned channel estimation matrix. The proposed method can suppress the above effects by means of CCI cancellation and successive channel estimation. Computer simulation confirms that the proposed channel estimation method can accurately estimate the channel, and the receiver with iterative equalization and the proposed method achieves excellent decoding performance in a MIMO-SM system.</p>]]></description>
<dc:creator><![CDATA[HIGASHINAKA, M., KUBO, H., OKAZAKI, A., OGAWA, Y., OHGANE, T., NISHIMURA, T.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2787</dc:identifier>
<dc:title><![CDATA[Soft Decision Directed Channel Estimation with Interference Cancellation for a MIMO System Using Iterative Equalization and Decoding]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2797</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2787</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Communication Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2798?rss=1">
<title><![CDATA[BER Performance Evaluation in 2 x 2 MIMO Spatial Multiplexing Systems under Rician Fading Channels]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2798?rss=1</link>
<description><![CDATA[<p>In this paper, BER (Bit Error Rate) performance in 2 <FONT FACE="arial,helvetica">x</FONT> 2 MIMO (Multiple-Input Multiple-Output) spatial multiplexing systems under Rician fading channels is evaluated. We examine BER performances employing inverse channel detection (ICD) under Rician fading channels, adding the phase of the direct path and Rician factor as a parameter. The results clearly indicate that the phase of the direct path and Rician factor have a great influence on BER performances employing ICD under Rician fading channels.</p>]]></description>
<dc:creator><![CDATA[MURAKAMI, Y., MATSUOKA, T., ORIHASHI, M.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2798</dc:identifier>
<dc:title><![CDATA[BER Performance Evaluation in 2 x 2 MIMO Spatial Multiplexing Systems under Rician Fading Channels]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2807</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2798</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Communication Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2808?rss=1">
<title><![CDATA[Analysis and Approximation of Statistical Distribution of Eigenvalues in i.i.d. MIMO Channels under Rayleigh Fading]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2808?rss=1</link>
<description><![CDATA[<p>In multiple input multiple output (MIMO) communication systems, eigenvalues of channel correlation matrices play an essential role for the performance analysis, and particularly the investigation about their behavior under time-variant environment ruled by a certain statistics is an important problem. This paper first gives the theoretical expressions for the marginal distributions of all the ordered eigenvalues of MIMO correlation matrices under i.i.d. (independent and identically distributed) Rayleigh fading environment. Then, an approximation method of those marginal distributions is presented: We show that the theory of SIMO space diversity using maximal ratio combining (MRC) is applicable to the approximation of statistical distributions of all eigenvalues in MIMO systems with the same number of diversity branches. The derived approximation has a monomial form suitable for the calculation of various performance measures utilized in MIMO systems. Through computer simulations, the effectiveness of the proposed method is demonstrated.</p>]]></description>
<dc:creator><![CDATA[TANIGUCHI, T., SHA, S., KARASAWA, Y.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2808</dc:identifier>
<dc:title><![CDATA[Analysis and Approximation of Statistical Distribution of Eigenvalues in i.i.d. MIMO Channels under Rayleigh Fading]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2817</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2808</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Communication Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2818?rss=1">
<title><![CDATA[Capacity Analysis of MIMO Rayleigh Channel with Spatial Fading Correlation]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2818?rss=1</link>
<description><![CDATA[<p>MIMO (Multiple Input Multiple Output) communications systems equipped with array antennas at both the transmitter and receiver sides are a promising scheme to realize higher rate and/or reliable data transmission. In this paper, capacity analysis of MIMO Rayleigh channel with spatial correlation at the receiver of multipath taken into account is presented. In general, a model configuration of local scattering around a mobile station in MIMO environment is carried out by simulation to examine spatial correlation coefficients. Based on statistical properties of the eigenvalues of correlated complex random Wishart matrices, the exact closed-form expressions of distribution of the eigenvalues are investigated. Then, the general closed-form evaluation of integral form is proposed based on Meijer's <I>G</I>-function. The results demonstrate that the ergodic capacities are improved by increasing the number of the antennas and the SNR's. Compared with i.i.d. (independent identically distributed) Rayleigh channel, the incremental improvement of correlated Rayleigh channel is reduced by spatial fading correlation. The analytical results validated by Monte-Carlo simulations show a good agreement.</p>]]></description>
<dc:creator><![CDATA[TRUNG, H. D., BENJAPOLAKUL, W., ARAKI, K.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2818</dc:identifier>
<dc:title><![CDATA[Capacity Analysis of MIMO Rayleigh Channel with Spatial Fading Correlation]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2826</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2818</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Communication Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2827?rss=1">
<title><![CDATA[Fair End-to-End Session Rates in Multihop Wireless Networks]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2827?rss=1</link>
<description><![CDATA[<p>This paper considers a proportional fairness of end-to-end session rates in a multihop wireless network through the rate control framework. In multihop wireless networks, there are two classes of rate control problem. One focuses in optimizing the transmission attempt probabilities at the lower layers, but not the transmit powers while other problem is closely related to jointly optimal congestion control and power control. Proportional fairness is a fundamental concept in flow control problems. In this paper, we give in-depth analysis and show that the optimal solutions of these problems are proportionally fair provided that the objective functions are suitably chosen.</p>]]></description>
<dc:creator><![CDATA[HWANG, W.-J., LE, C.-L.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2827</dc:identifier>
<dc:title><![CDATA[Fair End-to-End Session Rates in Multihop Wireless Networks]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2832</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2827</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Communication Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2833?rss=1">
<title><![CDATA[Generalized Scalar Multiplication Secure against SPA, DPA, and RPA]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2833?rss=1</link>
<description><![CDATA[<p>In the execution on a smart card, elliptic curve cryptosystems have to be secure against side channel attacks such as the simple power analysis (SPA), the differential power analysis (DPA), and the refined power analysis (RPA), and so on. MMM-algorithm proposed by Mamiya, Miyaji, and Morimoto is a scalar multiplication algorithm secure against SPA, DPA, and RPA, which can decrease the computational complexity by increasing the size of a pre-computed table. However, it provides only 4 different cases of pre-computed tables. From the practical point of view, a wider range of time-memory tradeoffs is usually desired. This paper generalizes MMM-algorithm to improve the flexibility of tables as well as the computational complexity. Our improved algorithm is secure, efficient and flexible for the storage size.</p>]]></description>
<dc:creator><![CDATA[MIYAJI, A.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2833</dc:identifier>
<dc:title><![CDATA[Generalized Scalar Multiplication Secure against SPA, DPA, and RPA]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2842</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2833</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Cryptography and Information Security</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2843?rss=1">
<title><![CDATA[A More Compact Representation of XTR Cryptosystem]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2843?rss=1</link>
<description><![CDATA[<p>XTR is one of the most efficient public-key cryptosystems that allow us to compress the communication bandwidth of their ciphertext. The compact representation can be achieved by deploying a subgroup F<SUB>q<sup>2</sup></SUB> of extension field F<SUB>q<sup>6</sup></SUB>, so that the compression ratio of XTR cryptosystem is 1/3. On the other hand, Dijk <I>et al</I>. proposed an efficient public-key cryptosystem using a torus over F<SUB>q<sup>30</sup></SUB> whose compression ratio is 4/15. It is an open problem to construct an efficient public-key cryptosystem whose compression ratio is smaller than 4/15. In this paper we propose a new variant of XTR cryptosystem over finite fields with characteristic three whose compression ratio is 1/6. The key observation is that there exists a trace map from F<SUB>q<sup>6</sup></SUB> to F<SUB>q</SUB> in the case of characteristic three. Moreover, the cost of compression and decompression algorithm requires only about 1% overhead compared with the original XTR cryptosystem. Therefore, the proposed variant of XTR cryptosystem is one of the fastest public-key cryptosystems with the smallest compression ratio.</p>]]></description>
<dc:creator><![CDATA[SHIRASE, M., HAN, D.-G., HIBINO, Y., KIM, H., TAKAGI, T.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2843</dc:identifier>
<dc:title><![CDATA[A More Compact Representation of XTR Cryptosystem]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2850</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2843</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Cryptography and Information Security</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2851?rss=1">
<title><![CDATA[Compression Functions Suitable for the Multi-Property-Preserving Transform]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2851?rss=1</link>
<description><![CDATA[<p>Since Bellare and Ristenpart showed a multi-property preserving domain extension transform, the problem of the construction for multi-property hash functions has been reduced to that of the construction for multi-property compression functions. However, the Davies-Meyer compression function that is commonly used for standard hash functions is not a multi-property compression function. That is, in the ideal cipher model, the Davies-Meyer compression function is collision resistant, but it is not indifferentiable from a random oracle. In this paper, we show that the compression function proposed by Lai and Massey is a multi-property compression function. In addition, we show that the simplified version of the Lai-Massey compression function is also a multi-property compression function. The use of these compression functions enables us to construct multi-property hash functions by the multi-property preserving domain extension transform.</p>]]></description>
<dc:creator><![CDATA[KUWAKADO, H., MORII, M.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2851</dc:identifier>
<dc:title><![CDATA[Compression Functions Suitable for the Multi-Property-Preserving Transform]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2859</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2851</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Cryptography and Information Security</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2860?rss=1">
<title><![CDATA[Efficient Secret Sharing Schemes Based on Unauthorized Subsets]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2860?rss=1</link>
<description><![CDATA[<p>We propose two multiple assignment secret sharing schemes realizing general access structures. One is always more efficient than the secret sharing scheme proposed by Ito, Saito and Nishizeki [5] from the viewpoint of the number of shares distributed to each participant. The other is also always more efficient than the scheme I of [7].</p>]]></description>
<dc:creator><![CDATA[TOCHIKUBO, K.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2860</dc:identifier>
<dc:title><![CDATA[Efficient Secret Sharing Schemes Based on Unauthorized Subsets]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2867</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2860</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Papers -- Cryptography and Information Security</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2868?rss=1">
<title><![CDATA[On the Suboptimality of Linear Lossy Codes]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2868?rss=1</link>
<description><![CDATA[<p>This letter reveals that linear lossy codes cannot attain the rate-distortion function in general, even if the source is binary i.i.d. and the distortion is measured by the Hamming distortion measure.</p>]]></description>
<dc:creator><![CDATA[KUZUOKA, S.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2868</dc:identifier>
<dc:title><![CDATA[On the Suboptimality of Linear Lossy Codes]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2869</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2868</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Letters -- Information Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2870?rss=1">
<title><![CDATA[Key Rate Available from Mismatched Measurements in the BB84 Protocol and the Uncertainty Principle]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2870?rss=1</link>
<description><![CDATA[<p>We consider the mismatched measurements in the BB84 quantum key distribution protocol, in which measuring bases are different from transmitting bases. We give a lower bound on the amount of a secret key that can be extracted from the mismatched measurements. Our lower bound shows that we can extract a secret key from the mismatched measurements with certain quantum channels, such as the channel over which the Hadamard matrix is applied to each qubit with high probability. Moreover, the entropic uncertainty principle implies that one cannot extract the secret key from both matched measurements and mismatched ones simultaneously, when we use the standard information reconciliation and privacy amplification procedure.</p>]]></description>
<dc:creator><![CDATA[MATSUMOTO, R., WATANABE, S.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2870</dc:identifier>
<dc:title><![CDATA[Key Rate Available from Mismatched Measurements in the BB84 Protocol and the Uncertainty Principle]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2873</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2870</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Letters -- Information Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2874?rss=1">
<title><![CDATA[Multiple Scaling Extrinsic Soft Information for Improved Min-Sum Iterative Decoding of LDPC Codes]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2874?rss=1</link>
<description><![CDATA[<p>This paper presents an improved min-sum iterative decoding scheme for regular and irregular LDPC codes. The proposed decoding scheme scales the extrinsic soft information from variable nodes to check. Different scaling factors are applied for iterations and the scaling factors are obtained by a simplified vector optimization method.</p>]]></description>
<dc:creator><![CDATA[LEE, C. H., KO, Y. C., HEO, J.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2874</dc:identifier>
<dc:title><![CDATA[Multiple Scaling Extrinsic Soft Information for Improved Min-Sum Iterative Decoding of LDPC Codes]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2876</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2874</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Letters -- Coding Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2877?rss=1">
<title><![CDATA[Theoretical Analysis of Bit Error Probability for 4-State Convolutional Code with Max-Log MAP Decoding]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2877?rss=1</link>
<description><![CDATA[<p>In this letter, a theoretical analysis of bit error probability for 4-state convolutional code with Max-Log-maximum a posteriori probability (MAP) decoding is presented. This technique employs an iterative calculation of probability density function of the state metric per one transition, and gives the exact bit error probability for all signal-to-noise power ratio.</p>]]></description>
<dc:creator><![CDATA[YOSHIKAWA, H.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2877</dc:identifier>
<dc:title><![CDATA[Theoretical Analysis of Bit Error Probability for 4-State Convolutional Code with Max-Log MAP Decoding]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2880</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2877</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Letters -- Coding Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2881?rss=1">
<title><![CDATA[Properties of a Convoluted-Time and Code Division Multiple Access Communication Systems Based upon Complete Complementary Codes]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2881?rss=1</link>
<description><![CDATA[<p>A convoluted-time and code division multiple access (CT-CDMA) communication system based on complete complementary codes has been proposed. In this letter, the properties of this communication system are discussed and compared with those of the conventional CDMA systems using complete complementary codes.</p>]]></description>
<dc:creator><![CDATA[KOJIMA, T., AONO, M.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2881</dc:identifier>
<dc:title><![CDATA[Properties of a Convoluted-Time and Code Division Multiple Access Communication Systems Based upon Complete Complementary Codes]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2884</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2881</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Letters -- Spectrum Technologies</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2885?rss=1">
<title><![CDATA[Precoder for Chip-Interleaved CDMA Using Space-Time Block-Coding]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2885?rss=1</link>
<description><![CDATA[<p>We study the performances of a synchronous chip-interleaved, block spread (CIBS) code division multiple access (CDMA) with space-time block-coding (STBC) in the presence of frequency-selective fading. For providing the space diversity gain due to STBC, we introduce the optimum precoding for the STBC. Zero-forcing and minimum mean square error equalizers for CIBS-CDMA are derived. Simulation results confirm that the proposed precoder is valid under the frequency selective fading.</p>]]></description>
<dc:creator><![CDATA[KIMURA, Y., SHIBATA, K., SAKAI, T.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2885</dc:identifier>
<dc:title><![CDATA[Precoder for Chip-Interleaved CDMA Using Space-Time Block-Coding]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2888</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2885</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Letters -- Spectrum Technologies</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2889?rss=1">
<title><![CDATA[Security of a Class of Knapsack Public-Key Cryptosystems against Low-Density Attack]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2889?rss=1</link>
<description><![CDATA[<p>In 2003, Kobayashi et al. proposed a new class of knapsack public-key cryptosystems over Gaussian integer ring. This scheme using two-sequences as the public key. In 2005, Sakamoto and Hayashi proposed an improved version of Kobayashi's scheme. In this paper, we propose the knapsack PKC using <I>l</I>-sequences as the public key and present the low-density attack on it. We have described Schemes R and G for <I>l</I> = 2, in which the public keys are constructed over rational integer ring and over Gaussian integer ring, respectively. We discusses on the difference of the security against the low-density attack. We show that the security levels of Schemes R and G differ only slightly.</p>]]></description>
<dc:creator><![CDATA[NASAKO, T., MURAKAMI, Y., KASAHARA, M.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2889</dc:identifier>
<dc:title><![CDATA[Security of a Class of Knapsack Public-Key Cryptosystems against Low-Density Attack]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2892</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2889</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Letters -- Cryptography and Information Security</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2893?rss=1">
<title><![CDATA[Analysis and Improvement of an Anonymity Scheme for P2P Reputation Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2893?rss=1</link>
<description><![CDATA[<p>In 2006, Miranda et al. proposed an anonymity scheme to achieve peers' anonymity in Peer-to-Peer (P2P) reputation systems. In this paper, we show that this scheme can not achieve peers' anonymity in two cases. We also propose an improvement which solves the problem and improves the degree of anonymity.</p>]]></description>
<dc:creator><![CDATA[HAO, L.-m., LU, S.-n., YANG, S.-t., LIU, N., HUANG, Q.-s.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2893</dc:identifier>
<dc:title><![CDATA[Analysis and Improvement of an Anonymity Scheme for P2P Reputation Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2895</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2893</prism:startingPage>
<prism:section>Special Section on Information Theory and Its Applications -- Letters -- Cryptography and Information Security</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2896?rss=1">
<title><![CDATA[Special Section on Smart Multimedia & Communication Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2896?rss=1</link>
<description><![CDATA[]]></description>
<dc:creator><![CDATA[Taguchi, A., Onoye, T.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2896</dc:identifier>
<dc:title><![CDATA[Special Section on Smart Multimedia & Communication Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2896</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2896</prism:startingPage>
<prism:section>Special Section on Smart Multimedia  &amp;  Communication Systems</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2897?rss=1">
<title><![CDATA[StegErmelc: A Novel DCT-Based Steganographic Method Using Three Strategies]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2897?rss=1</link>
<description><![CDATA[<p>This paper proposes a DCT-based steganographic method named StegErmelc in the JPEG domain. Three strategies are proposed, namely (i) edge-like block selection, (ii) recursive matrix encoding, and (iii) largest coefficient serving, to form a novel steganographic method for achieving scalable carrier capacity, low detectability by universal blind steganalyzer, and high image quality, simultaneously. For a given message length, StegErmelc flexibly scales its carrier capacity to accommodate the message while trading off with stego detectability. At full capacity, StegErmelc has comparable carrier capacity relative to the existing methods. When embedding the same amount of information, StegErmelc remarkably reduces the stego detection rate to about 0.3&ndash;0.5 lower than that of the existing methods considered, and consequently StegErmelc can withstand blind steganalyzer when embedding up to 0.10 bpc. Under the same condition, StegErmelc produces stego image with quality higher than that of the existing methods considered. Graphical comparison with three additional evaluation metrics is also presented to show the relative performance of StegErmelc with respect to the existing methods considered.</p>]]></description>
<dc:creator><![CDATA[WONG, K., TANAKA, K.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2897</dc:identifier>
<dc:title><![CDATA[StegErmelc: A Novel DCT-Based Steganographic Method Using Three Strategies]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2908</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2897</prism:startingPage>
<prism:section>Special Section on Smart Multimedia  &amp;  Communication Systems -- Papers -- Image Security</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2909?rss=1">
<title><![CDATA[Implementation of Multi-Agent Object Attention System Based on Biologically Inspired Attractor Selection]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2909?rss=1</link>
<description><![CDATA[<p>A multi-agent object attention system is proposed, which is based on biologically inspired attractor selection model. Object attention is facilitated by using a video sequence and a depth map obtained through a compound-eye image sensor TOMBO. Robustness of the multi-agent system over environmental changes is enhanced by utilizing the biological model of adaptive response by attractor selection. To implement the proposed system, an efficient VLSI architecture is employed with reducing enormous computational costs and memory accesses required for depth map processing and multi-agent attractor selection process. According to the FPGA implementation result of the proposed object attention system, which is accomplished by using 7,063 slices, 640<FONT FACE="arial,helvetica">x</FONT>512 pixel input images can be processed in real-time with three agents at a rate of 9 fps in 48 MHz operation.</p>]]></description>
<dc:creator><![CDATA[HASHIMOTO, R., MATSUMURA, T., NOZATO, Y., WATANABE, K., ONOYE, T.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2909</dc:identifier>
<dc:title><![CDATA[Implementation of Multi-Agent Object Attention System Based on Biologically Inspired Attractor Selection]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2917</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2909</prism:startingPage>
<prism:section>Special Section on Smart Multimedia  &amp;  Communication Systems -- Papers -- Video Processing Systems</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2918?rss=1">
<title><![CDATA[An Image Completion Algorithm Using Occlusion-Free Images from Internet Photo Sharing Sites]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2918?rss=1</link>
<description><![CDATA[<p>In this paper, we propose an image completion algorithm which takes advantage of the countless number of images available on Internet photo sharing sites to replace occlusions in an input image. The algorithm 1) automatically selects the most suitable images from a database of downloaded images and 2) seamlessly completes the input image using the selected images with minimal user intervention. Experimental results on input images captured at various locations and scene conditions demonstrate the effectiveness of the proposed technique in seamlessly reconstructing user-defined occlusions.</p>]]></description>
<dc:creator><![CDATA[AMIRSHAHI, H., KONDO, S., ITO, K., AOKI, T.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2918</dc:identifier>
<dc:title><![CDATA[An Image Completion Algorithm Using Occlusion-Free Images from Internet Photo Sharing Sites]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2927</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2918</prism:startingPage>
<prism:section>Special Section on Smart Multimedia  &amp;  Communication Systems -- Papers -- Image Processing</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2928?rss=1">
<title><![CDATA[JPEG Compatible Raw Image Coding Based on Polynomial Tone Mapping Model]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2928?rss=1</link>
<description><![CDATA[<p>In this paper, we propose a coding method for camera raw images with high dynamic ranges. Our encoder has two layers. In the first layer, 24 bit low dynamic range image is encoded by a conventional codec, and then the residual image that represents the difference between the raw image and its approximation is encoded in the second layer. The approximation is derived by a polynomial fitting. The main advantage of this approach is that applying the polynomial model reduces the correlation between the raw and 24 bit images, which increases coding efficiency. Experiments shows compression efficiency is significantly improved by taking an inverse tone mapping into account.</p>]]></description>
<dc:creator><![CDATA[OKUDA, M., ADAMI, N.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2928</dc:identifier>
<dc:title><![CDATA[JPEG Compatible Raw Image Coding Based on Polynomial Tone Mapping Model]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2933</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2928</prism:startingPage>
<prism:section>Special Section on Smart Multimedia  &amp;  Communication Systems -- Papers -- Image Coding</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2934?rss=1">
<title><![CDATA[Macroblock Feature Based Complexity Reduction for H.264/AVC Motion Estimation]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2934?rss=1</link>
<description><![CDATA[<p>In H.264/AVC standard, many new techniques such as variable block size (VBS) and multiple reference frame (MRF) are used in motion estimation (ME) part to achieve superior coding performance. However, the use of new techniques will also cause great burden on computation complexity, which leads to problems in low power hardware implementation. Many software based fast ME algorithms are proposed to reduce complexity. For real-time hardwired encoder, the huge throughput of fractional motion estimation (FME) and integer motion estimation (IME) makes pipeline stage a must. In this case, IME is arranged in a single stage, which deteriorates the efficiency of many software based algorithms. Based on the hardware data flow, this paper provides a complexity reduction algorithm which speeds up ME procedure through three schemes. Firstly, the proposed algorithm executes similarity analysis to detect big mode MB and apply early termination in IME stage. Secondly, for normal MB, motion feature is extracted after IME of each frame and a 6-ring based search range adjustment scheme is introduced to remove redundant search positions. Thirdly, for MBs which have large motion feature, the pixel difference is very small due to the blur effect on video sensor. So, we use subsampling technique to reduce computation complexity for such MBs. Experimental results show that, compared with hardware friendly full search algorithm, the proposed fast ME algorithm can reduce 52.63% to 83.21% ME time with negligible video quality degradation. Furthermore, since the proposed algorithm works in a hardware friendly way, it can be embedded into 3-stage real-time hardwired video encoder to achieve low power design.</p>]]></description>
<dc:creator><![CDATA[HUANG, Y., LIU, Q., IKENAGA, T.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2934</dc:identifier>
<dc:title><![CDATA[Macroblock Feature Based Complexity Reduction for H.264/AVC Motion Estimation]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2944</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2934</prism:startingPage>
<prism:section>Special Section on Smart Multimedia  &amp;  Communication Systems -- Papers -- Video Coding</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2945?rss=1">
<title><![CDATA[Variable Block Size Motion Vector Retrieval Schemes for H.264 Inter Frame Error Concealment]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2945?rss=1</link>
<description><![CDATA[<p>With the ubiquitous application of Internet and wireless networks, H.264 video communication becomes more and more common. However, due to the high-efficiently predictive coding and the variable length entropy coding, it is more sensitive to transmission errors. The current error concealment (EC) scheme, which utilizes the spatial and temporal correlations to conceal the corrupted region, produces unsatisfied boundary artifacts. In this paper, first we propose variable block size error concealment (VBSEC) scheme inspired by variable block size motion estimation (VBSME) in H.264. This scheme provides four EC modes and four sub-block partitions. The whole corrupted macro-block (MB) will be divided into variable block size adaptively according to the actual motion. More precise motion vectors (MV) will be predicted for each sub-block. Then MV refinement (MVR) scheme is proposed to refine the MV of the heterogeneous sub-block by utilizing three step search (TSS) algorithm adaptively. Both VBSEC and MVR are based on our directional spatio-temporal boundary matching algorithm (DSTBMA). By utilizing these schemes, we can reconstruct the corrupted MB in the inter frame more accurately. The experimental results show that our proposed scheme can obtain better objective and subjective EC quality, respectively compared with the boundary matching algorithm (BMA) adopted in the JM11.0 reference software, spatio-temporal boundary matching algorithm (STBMA) and other comparable EC methods.</p>]]></description>
<dc:creator><![CDATA[WANG, L., WANG, J., GOTO, S., IKENAGA, T.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2945</dc:identifier>
<dc:title><![CDATA[Variable Block Size Motion Vector Retrieval Schemes for H.264 Inter Frame Error Concealment]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2953</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2945</prism:startingPage>
<prism:section>Special Section on Smart Multimedia  &amp;  Communication Systems -- Papers -- Video Coding</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2954?rss=1">
<title><![CDATA[Standard Deviation and Intra Prediction Mode Based Adaptive Spatial Error Concealment (SEC) in H.264/AVC]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2954?rss=1</link>
<description><![CDATA[<p>Transmission of compressed video over error prone channels may result in packet losses or errors, which can significantly degrade the image quality. Therefore an error concealment scheme is applied at the video receiver side to mask the damaged video. Considering there are 3 types of MBs (Macro Blocks) in natural video frame, i.e., Textural MB, Edged MB, and Smooth MB, this paper proposes an adaptive spatial error concealment which can choose 3 different methods for these 3 different MBs. For criteria of choosing appropriate method, 2 factors are taken into consideration. Firstly, standard deviation of our proposed edge statistical model is exploited. Secondly, some new features of latest video compression standard H.264/AVC, i.e., intra prediction mode is also considered for criterion formulation. Compared with previous works, which are only based on deterministic measurement, proposed method achieves the best image recovery. Subjective and objective image quality evaluations in experiments confirmed this.</p>]]></description>
<dc:creator><![CDATA[WANG, J., WANG, L., IKENAGA, T., GOTO, S.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2954</dc:identifier>
<dc:title><![CDATA[Standard Deviation and Intra Prediction Mode Based Adaptive Spatial Error Concealment (SEC) in H.264/AVC]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2962</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2954</prism:startingPage>
<prism:section>Special Section on Smart Multimedia  &amp;  Communication Systems -- Papers -- Video Coding</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2963?rss=1">
<title><![CDATA[Minimum Kullback-Leibler-Based Turbo Multiuser Detector over Decomposition CDMA Signal]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2963?rss=1</link>
<description><![CDATA[<p>In this paper, we develop a new iterative turbo multiuser detector for direct sequence code-division multiple access (DS-CDMA) systems over unknown frequency-selective channels by decomposing the observation signal into a number of signal components. Virtual trellis model representing the ISI channel for each separating signal user is designed to generate extrinsic probability in term of BCJR algorithm for exchange with a single channel decoder as priori information. Minimum kullback-leibler (MKL) framework is derived to calculate numerical channel estimation and extrinsic probability. In comparison with other similar receiver, simulation results demonstrate that the proposed solution achieves the desirable performance.</p>]]></description>
<dc:creator><![CDATA[PLOYSUWAN, T., TANTIPHANWADI, S., TEEKAPUT, P.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2963</dc:identifier>
<dc:title><![CDATA[Minimum Kullback-Leibler-Based Turbo Multiuser Detector over Decomposition CDMA Signal]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2972</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2963</prism:startingPage>
<prism:section>Special Section on Smart Multimedia  &amp;  Communication Systems -- Papers -- DS-CDMA</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2973?rss=1">
<title><![CDATA[New PAPR Reduction in OFDM System Using Hybrid of PTS-APPR Methods with Coded Side Information Technique]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2973?rss=1</link>
<description><![CDATA[<p>In this paper, we propose a new PAPR reduction by using the hybrid of a partial transmit sequences (PTS) and an adaptive peak power reduction (APPR) methods with coded side information (SI) technique. These methods are used in an Orthogonal Frequency Division Multiplexing (OFDM) system. The OFDM employs orthogonal sub-carriers for data modulation. These sub-carriers unexpectedly present a large Peak to Average Power Ratio (PAPR) in some cases. In order to reduce PAPR, the sequence of input data is rearranged by PTS. The APPR method is also used to controls the peak level of modulation signals by an adaptive algorithm. A proposed reduction method consists of these two methods and realizes both advantages at the same time. In order to make the optimum condition on PTS for PAPR reduction, a quite large calculation cost must be demanded and thus it is impossible to obtain the optimum PTS. In the proposed method, by using the pseudo-optimum condition with a coded SI technique, the total calculation cost becomes drastically reduced. In simulation results, the proposed method shows the improvement on PAPR and also reveals the high performance on bit error rate (BER) of an OFDM system.</p>]]></description>
<dc:creator><![CDATA[PRADABPET, C., YOSHIZAWA, S., MIYANAGA, Y., DEJHAN, K.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2973</dc:identifier>
<dc:title><![CDATA[New PAPR Reduction in OFDM System Using Hybrid of PTS-APPR Methods with Coded Side Information Technique]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2979</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2973</prism:startingPage>
<prism:section>Special Section on Smart Multimedia  &amp;  Communication Systems -- Papers -- OFDM</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2980?rss=1">
<title><![CDATA[A Novel Chaotic Multiple-Bits Modulation Scheme Using Mapping Parameters as Data Carrier]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2980?rss=1</link>
<description><![CDATA[<p>This paper proposes a novel chaotic multiple-bits modulation scheme that uses the parameters in the map as data carrier for chaotic digital communication. Chaotic signals modulated with the parameters corresponding to the information to be transmitted are sent to the receiver. The information sent to the receiver can be decoded by a correlation detector. This scheme can increase the number of transmittable information bit per unit carrier signals by increasing the number of mapping parameters to be used for modulation. We verify the performance of this scheme using bit error rate (BER) through computer simulation. Also, we compare the performance of the proposed method with a conventional single-bit modulation scheme.</p>]]></description>
<dc:creator><![CDATA[YANO, K., TANAKA, K.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2980</dc:identifier>
<dc:title><![CDATA[A Novel Chaotic Multiple-Bits Modulation Scheme Using Mapping Parameters as Data Carrier]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2989</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2980</prism:startingPage>
<prism:section>Special Section on Smart Multimedia  &amp;  Communication Systems -- Papers -- Chaotic Communication</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2990?rss=1">
<title><![CDATA[New Minimum Decoding Complexity Quasi-Orthogonal Space-Time Block Code for 8 Transmit Antennas]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2990?rss=1</link>
<description><![CDATA[<p>In this paper, a new full-rate space-time block code (STBC) possessing a quasi-orthogonal (QO) property is proposed for QAM and 8 transmit antennas. This code is designed by serially concatenating a real constellation-rotating precoder with the Alamouti scheme. The QO property enables ML decoding to be done with joint detection of only four real symbols like the conventional minimum decoding complexity QO-STBC (MDC-QO-STBC). However, the proposed code is guaranteed to achieve full spatial diversity for general QAM unlike the MDC-QO-STBC which is specifically presented for only 4-QAM. By computer simulation results, we show that the proposed code exhibits the identical and slightly degraded error performance with the MDC-QO-STBC for 4-QAM and the Sharma's QO-STBC for 4 and 16-QAM, respectively. Finally, we present a new modified scheme of the original code so that there is no any discontinuity of transmission at each transmit antenna, without any loss of error performance.</p>]]></description>
<dc:creator><![CDATA[CHAE, C., CHOI, D., JUNG, T.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2990</dc:identifier>
<dc:title><![CDATA[New Minimum Decoding Complexity Quasi-Orthogonal Space-Time Block Code for 8 Transmit Antennas]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>2994</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2990</prism:startingPage>
<prism:section>Special Section on Smart Multimedia  &amp;  Communication Systems -- Papers -- MIMO</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2995?rss=1">
<title><![CDATA[S3: Smart Session Selection for Voice Communications in Next Generation Wireless Network]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/2995?rss=1</link>
<description><![CDATA[<p>Selecting transparently a proper network connection for voice communication will be a fundamental requirement in future multi-mode heterogeneous wireless network. This paper presented a smart session selection (S<sup>3</sup>) scheme to meet this requirement. Instead of selecting a best access network as in conventional Always Best Connected (ABC) paradigm, S<sup>3</sup> enables users to select a best network connection, which consists of source and destination access network pair, to satisfy quality constraint and users' preference. To support S<sup>3</sup>, we develop a user profile to specify network connection priority. Meanwhile IP multimedia subsystem (IMS) is extended to make smart decision for users. Finally, Analytic Hierarchy Process (AHP) is used to recommend a network connection with assistance of user profile and IMS signaling. An example is illustrated to show that AHP can successfully select a good network connection that fulfills the requirement of users.</p>]]></description>
<dc:creator><![CDATA[CHUNG, T.-Y., YUAN, F.-C., CHEN, Y.-M., LIU, B.-J.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.2995</dc:identifier>
<dc:title><![CDATA[S3: Smart Session Selection for Voice Communications in Next Generation Wireless Network]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3002</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>2995</prism:startingPage>
<prism:section>Special Section on Smart Multimedia  &amp;  Communication Systems -- Papers -- Mobile Multimedia Communication</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3003?rss=1">
<title><![CDATA[Dynamic Two-Tier Cell Structure for Bandwidth Reservation of Handoffs in Cellular Networks]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3003?rss=1</link>
<description><![CDATA[<p>To satisfy both the bandwidth efficiency of low-speed mobile hosts (MHs) and seamless handoff of high-speed MHs in cellular networks, this paper proposes a reservation scheme which exploits a dynamic two-tier cell structure and the handoff probability. The dynamic two-tier cell structure determines the reservation and non-reservation zones according to the speed of MHs. The handoff probability is calculated using the moving speed and the direction of MHs.</p>]]></description>
<dc:creator><![CDATA[PARK, J. K., LEE, W. Y., HONG, S. J., KIM, J.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.3003</dc:identifier>
<dc:title><![CDATA[Dynamic Two-Tier Cell Structure for Bandwidth Reservation of Handoffs in Cellular Networks]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3005</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>3003</prism:startingPage>
<prism:section>Special Section on Smart Multimedia  &amp;  Communication Systems -- Letter -- Mobile Information Network</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3006?rss=1">
<title><![CDATA[An Estimation Method of Parameters for Closed-box Loudspeaker System]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3006?rss=1</link>
<description><![CDATA[<p>In this paper, we propose a method that uses Simulated Annealing (SA) to estimate the linear and nonlinear parameters of a closed-box loudspeaker system for implementing effective Mirror filters. The nonlinear parameters determined by W. Klippel's method are sometimes inaccurate and imaginary. In contrast, the proposed method can estimate the parameters with satisfactory accuracy due to its use of SA; the resulting impedance and displacement characteristics match those of an actual equivalent loudspeaker. A Mirror filter designed around these parameters can well compensate the nonlinear distortions of the loudspeaker system. Experiments demonstrate that the method can reduce the levels of nonlinear distortion by 5 dB to 20 dB compared to the before compensation condition.</p>]]></description>
<dc:creator><![CDATA[NAKAO, R., KAJIKAWA, Y., NOMURA, Y.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.3006</dc:identifier>
<dc:title><![CDATA[An Estimation Method of Parameters for Closed-box Loudspeaker System]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3013</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>3006</prism:startingPage>
<prism:section>Regular Section -- Papers -- Engineering Acoustics</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3014?rss=1">
<title><![CDATA[Gramian-Preserving Frequency Transformation for Linear Discrete-Time State-Space Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3014?rss=1</link>
<description><![CDATA[<p>This paper proposes the Gramian-preserving frequency transformation for linear discrete-time state-space systems. In this frequency transformation, we replace each delay element of a discrete-time system with an allpass system that has a balanced realization. This approach can generate transformed systems that have the same controllability/observability Gramians as those of the original system. From this result, we show that the Gramian-preserving frequency transformation gives us transformed systems with different magnitude characteristics, but with the same structural property with respect to the Gramians as that of the original system. This paper also presents a simple method for realization of the Gramian-preserving frequency transformation. This method makes use of the cascaded normalized lattice structure of allpass systems.</p>]]></description>
<dc:creator><![CDATA[KOSHITA, S., TANAKA, S., ABE, M., KAWAMATA, M.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.3014</dc:identifier>
<dc:title><![CDATA[Gramian-Preserving Frequency Transformation for Linear Discrete-Time State-Space Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3021</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>3014</prism:startingPage>
<prism:section>Regular Section -- Papers -- Systems and Control</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3022?rss=1">
<title><![CDATA[Recursive Computation of Static Output Feedback Stochastic Nash Games for Weakly-Coupled Large-Scale Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3022?rss=1</link>
<description><![CDATA[<p>This paper discusses the infinite horizon static output feedback stochastic Nash games involving state-dependent noise in weakly coupled large-scale systems. In order to construct the strategy, the conditions for the existence of equilibria have been derived from the solutions of the sets of cross-coupled stochastic algebraic Riccati equations (CSAREs). After establishing the asymptotic structure along with the positive semidefiniteness for the solutions of CSAREs, recursive algorithm for solving CSAREs is derived. As a result, it is shown that the proposed algorithm attains the reduced-order computations and the reduction of the CPU time. As another important contribution, the uniqueness of the strategy set is proved for the sufficiently small parameter . Finally, in order to demonstrate the efficiency of the proposed algorithm, numerical example is given.</p>]]></description>
<dc:creator><![CDATA[SAGARA, M., MUKAIDANI, H., YAMAMOTO, T.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.3022</dc:identifier>
<dc:title><![CDATA[Recursive Computation of Static Output Feedback Stochastic Nash Games for Weakly-Coupled Large-Scale Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3029</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>3022</prism:startingPage>
<prism:section>Regular Section -- Papers -- Systems and Control</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3030?rss=1">
<title><![CDATA[A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3030?rss=1</link>
<description><![CDATA[<p>Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation while maintaining the circuit behavior and topology. However, if the minimum feasible clock period is reduced, then the number of registers tends to be increased. In this paper, we propose a gate-level register relocation method that reduces the number of registers while keeping the target clock period. In experiments, the proposed method reduces the number of registers in the practical time in most circuits.</p>]]></description>
<dc:creator><![CDATA[KOHIRA, Y., TAKAHASHI, A.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.3030</dc:identifier>
<dc:title><![CDATA[A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3037</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>3030</prism:startingPage>
<prism:section>Regular Section -- Papers -- VLSI Design Technology and CAD</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3038?rss=1">
<title><![CDATA[Arithmetic Circuit Verification Based on Symbolic Computer Algebra]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3038?rss=1</link>
<description><![CDATA[<p>This paper presents a formal approach to verify arithmetic circuits using symbolic computer algebra. Our method describes arithmetic circuits directly with high-level mathematical objects based on weighted number systems and arithmetic formulae. Such circuit description can be effectively verified by polynomial reduction techniques using Gr&ouml;bner Bases. In this paper, we describe how the symbolic computer algebra can be used to describe and verify arithmetic circuits. The advantageous effects of the proposed approach are demonstrated through experimental verification of some arithmetic circuits such as multiply-accumulator and FIR filter. The result shows that the proposed approach has a definite possibility of verifying practical arithmetic circuits.</p>]]></description>
<dc:creator><![CDATA[WATANABE, Y., HOMMA, N., AOKI, T., HIGUCHI, T.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.3038</dc:identifier>
<dc:title><![CDATA[Arithmetic Circuit Verification Based on Symbolic Computer Algebra]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3046</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>3038</prism:startingPage>
<prism:section>Regular Section -- Papers -- VLSI Design Technology and CAD</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3047?rss=1">
<title><![CDATA[Seven New Block Cipher Structures with Provable Security against Differential Cryptanalysis]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3047?rss=1</link>
<description><![CDATA[<p>The design and analysis of block ciphers is an established field of study which has seen significant progress since the early 1990s. Nevertheless, what remains on an interesting direction to explore in this area is to design block ciphers with provable security against powerful known attacks such as differential and linear cryptanalysis. In this paper we introduce seven new block cipher structures, named Feistel-variant A, B, CLEFIA and MISTY-FO-variant A, B, C, D structures, and show that these structures are provably resistant against differential cryptanalysis. The main results of this paper are that the average differential probabilities over at least 2 rounds of Feistel-variant A structure and 1 round of Feistel-variant B structure are both upperbounded by <I>p</I><sup>2</sup>, while the average differential probabilities over at least 5 rounds of CLEFIA, MISTY-FO-variant A, B, C and D structures are upperbounded by <I>p</I><sup>4</sup> + 2<I>p</I><sup>5</sup>, <I>p</I><sup>4</sup>, <I>p</I><sup>4</sup>, 2<I>p</I><sup>4</sup> and 2<I>p</I><sup>4</sup>, respectively, if the maximum differential probability of a round <I>F</I> function is <I>p</I>. We also give provable security for the Feistel-variant A, B and CLEFIA structures against linear cryptanalysis. Our results are attained under the assumption that all of components in our proposed structures are bijective. We expect that our results are useful to design block ciphers with provable security against differential and linear cryptanalysis.</p>]]></description>
<dc:creator><![CDATA[KIM, J., LEE, C., SUNG, J., HONG, S., LEE, S., LIM, J.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.3047</dc:identifier>
<dc:title><![CDATA[Seven New Block Cipher Structures with Provable Security against Differential Cryptanalysis]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3058</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>3047</prism:startingPage>
<prism:section>Regular Section -- Papers -- Cryptography and Information Security</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3059?rss=1">
<title><![CDATA[Azimuthal and Elevation Localization Using Inter-Channel Phase and Level Differences for a Hemispheric Object]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3059?rss=1</link>
<description><![CDATA[<p>The frequency domain binaural model (FDBM) has been previously proposed to localize multiple sound sources. Since the method requires only two input signals and uses interaural phase and level differences caused by the diffraction generated by the head, flexibility in application is very high when the head is considered as an object. When an object is symmetric with respect to the two microphones, the performance of sound source localization is degraded, as a human being has front-back confusion due to the symmetry in a median plane. This paper proposes to reduce the degradation of performance on sound source localization by a combination of the microphone pair outputs using the FDBM. The proposed method is evaluated by applying to a security camera system, and the results showed performance improvement in sound source localization because of reducing the number of cones of confusion.</p>]]></description>
<dc:creator><![CDATA[CHISAKI, Y., TAKADA, T., NAGANISHI, M., USAGAWA, T.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.3059</dc:identifier>
<dc:title><![CDATA[Azimuthal and Elevation Localization Using Inter-Channel Phase and Level Differences for a Hemispheric Object]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3062</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>3059</prism:startingPage>
<prism:section>Regular Section -- Letters -- Engineering Acoustics</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3063?rss=1">
<title><![CDATA[Research on Channel Quantization Algorithm of Time Correlated Channels]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3063?rss=1</link>
<description><![CDATA[<p>Focusing on time correlation of real communication channels, a channel quantization algorithm based on finite state vector quantization (FSVQ) is proposed. Firstly channels are partitioned into finite states, then codebooks corresponding to each state are constructed, which are used to quantize channels transferred from corresponding states. Further, the state transition function is designed to ensure the synchronization between transmitter and receiver. The proposed algorithm can achieve improved performance with the same feedback load compared with classical memoryless channel quantizer without consideration of the influence of time correlation. Simulation results verify the effectiveness of the proposed algorithm.</p>]]></description>
<dc:creator><![CDATA[FENG, Z., ZHANG, T., ZENG, E.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.3063</dc:identifier>
<dc:title><![CDATA[Research on Channel Quantization Algorithm of Time Correlated Channels]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3066</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>3063</prism:startingPage>
<prism:section>Regular Section -- Letters -- Digital Signal Processing</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3067?rss=1">
<title><![CDATA[A Multiple-Mask Operation Compatible with IEEE 802.15.4a Non-coherent UWB Ranging Systems]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3067?rss=1</link>
<description><![CDATA[<p>During the execution of precise ranging in the time domain, the most important fact to consider is how to achieve an accurate estimate of the time corresponding to first arrival of the transmitter. However, it is difficult to extract an estimate of the time-of-arrival (TOA) through use of a simple correlator due to degradation on correlation, and in the case where the pulse repetition interval (PRI) is less than the maximum excess delay (MED). In order to enhance the correlation capability, this paper proposes a TOA estimation method that obeys a threshold predetermined in a non-coherent system using multiple-mask operation (MMO). The performance of the proposed scheme is verified by conducting simulations under two different types of channel situations. The simulation results show that the proposed scheme performs well even in a dense indoor multipath environment and with the existence of multiple simultaneously operating piconets (SOPs).</p>]]></description>
<dc:creator><![CDATA[PARK, W.-Y., CHOI, S., LEE, W.-C.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.3067</dc:identifier>
<dc:title><![CDATA[A Multiple-Mask Operation Compatible with IEEE 802.15.4a Non-coherent UWB Ranging Systems]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3070</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>3067</prism:startingPage>
<prism:section>Regular Section -- Letters -- Digital Signal Processing</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3071?rss=1">
<title><![CDATA[Feedback Error Learning with Insufficient Excitation]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3071?rss=1</link>
<description><![CDATA[<p>This letter studies the tracking error in Multi-input Multi-output Feedback Error Learning (MIMO-FEL) system having insufficient excitation. It is shown that the error converges to zero exponentially even if the reference signal lacks the persistently excitation (PE) condition. Furthermore, by making full use of this fast convergence, we estimate the plant parameter while in operation based on frequency response. Simulation results show the effectiveness of the proposed method compared to a conventional approach.</p>]]></description>
<dc:creator><![CDATA[ALALI, B., HIRATA, K., SUGIMOTO, K.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.3071</dc:identifier>
<dc:title><![CDATA[Feedback Error Learning with Insufficient Excitation]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3075</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>3071</prism:startingPage>
<prism:section>Regular Section -- Letters -- Systems and Control</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3076?rss=1">
<title><![CDATA[Schedulability Analysis of Periodic and Sporadic Tasks Using a Timed Discrete Event Model with Memorable Events]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3076?rss=1</link>
<description><![CDATA[<p>In a real-time system, when the execution of a task is preempted by another task, the interrupted task falls into a blocked state. Since its re-execution begins from the interrupted point generally, the task's timer containing the remaining time until its completion should be maintained in the blocked state. This is the reason for introducing the notion of <I>memorable events</I> in this paper. We present a new timed discrete event model (TDEM) that adds the memorable events to the TDEM framework of Brandin and Wonham (1994). Using supervisory control theory upon the proposed TDEM, we analyze the schedulability of preemptable periodic and sporadic tasks executing on a uniprocessor.</p>]]></description>
<dc:creator><![CDATA[YANG, J.-M., PARK, S.-J.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.3076</dc:identifier>
<dc:title><![CDATA[Schedulability Analysis of Periodic and Sporadic Tasks Using a Timed Discrete Event Model with Memorable Events]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3079</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>3076</prism:startingPage>
<prism:section>Regular Section -- Letters -- Systems and Control</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3080?rss=1">
<title><![CDATA[Electronically Tunable High Input Impedance Voltage-Mode Multifunction Filter]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3080?rss=1</link>
<description><![CDATA[<p>A novel electronically tunable high input impedance voltage-mode multifunction filter with single inputs and three outputs employing two single-output-operational transconductance amplifiers, one differential difference current conveyor and two capacitors is proposed. The presented filter can be realized the highpass, bandpass and lowpass functions, simultaneously. The input of the filter exhibits high input impedance so that the synthesized filter can be cascaded without additional buffers. The circuit needs no any external resistors and employs two grounded capacitors, which is suitable for integrated circuit implementation.</p>]]></description>
<dc:creator><![CDATA[CHEN, H.-P., YANG, W.-S.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.3080</dc:identifier>
<dc:title><![CDATA[Electronically Tunable High Input Impedance Voltage-Mode Multifunction Filter]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3083</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>3080</prism:startingPage>
<prism:section>Regular Section -- Letters -- Circuit Theory</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3084?rss=1">
<title><![CDATA[All Pairings Are in a Group]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3084?rss=1</link>
<description><![CDATA[<p>In this paper, we suggest that all pairings are in a group from an abstract angle. Based on the results, some new pairings with the short Miller loop are constructed for great efficiency. It is possible that our observation can be applied into other aspects of pairing-based cryptosystems.</p>]]></description>
<dc:creator><![CDATA[ZHAO, C.-A., ZHANG, F., HUANG, J.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.3084</dc:identifier>
<dc:title><![CDATA[All Pairings Are in a Group]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3087</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>3084</prism:startingPage>
<prism:section>Regular Section -- Letters -- Cryptography and Information Security</prism:section>
</item>

<item rdf:about="http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3088?rss=1">
<title><![CDATA[MR-MIL: Manifold Ranking Based Multiple-Instance Learning for Automatic Image Annotation]]></title>
<link>http://ietfec.oxfordjournals.org/cgi/content/short/E91-A/10/3088?rss=1</link>
<description><![CDATA[<p>A novel automatic image annotation (AIA) scheme is proposed based on multiple-instance learning (MIL). For a given concept, manifold ranking (MR) is first employed to MIL (referred as MR-MIL) for effectively mining the positive instances (i.e. regions in images) embedded in the positive bags (i.e. images). With the mined positive instances, the semantic model of the concept is built by the probabilistic output of SVM classifier. The experimental results reveal that high annotation accuracy can be achieved at region-level.</p>]]></description>
<dc:creator><![CDATA[ZHAO, Y., ZHAO, Y., ZHU, Z., PAN, J.-S.]]></dc:creator>
<dc:date>2008-10-10</dc:date>
<dc:identifier>info:doi/10.1093/ietfec/e91-a.10.3088</dc:identifier>
<dc:title><![CDATA[MR-MIL: Manifold Ranking Based Multiple-Instance Learning for Automatic Image Annotation]]></dc:title>
<dc:publisher>The Institute of Electronics, Information and Communication Engineers</dc:publisher>
<prism:number>10</prism:number>
<prism:volume>E91-A</prism:volume>
<prism:endingPage>3089</prism:endingPage>
<prism:publicationDate>2008-10-01</prism:publicationDate>
<prism:startingPage>3088</prism:startingPage>
<prism:section>Regular Section -- Letters -- Image</prism:section>
</item>

</rdf:RDF>