IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Special Section on VLSI Design and CAD Algorithms

Hidetoshi Onodera

Special Section on VLSI Design and CAD Algorithms
IEICE Trans Fundamentals 2006 E89-A: 3377; doi:10.1093/ietfec/e89-a.12.3377 [PDF]  

Special Section on VLSI Design and CAD Algorithms -- Papers -- System Level Design

Hongwei ZHU, Ilie I. LUICAN, and Florin BALASA

Memory Size Computation for Real-Time Multimedia Applications Based on Polyhedral Decomposition
IEICE Trans Fundamentals 2006 E89-A: 3378-3386; doi:10.1093/ietfec/e89-a.12.3378 [Abstract] [PDF] [References]  

Thanyapat SAKUNKONCHAK, Satoshi KOMATSU, and Masahiro FUJITA

Synchronization Verification in System-Level Design with ILP Solvers
IEICE Trans Fundamentals 2006 E89-A: 3387-3396; doi:10.1093/ietfec/e89-a.12.3387 [Abstract] [PDF] [References]  

Yu LIU, Satoshi KOMATSU, and Masahiro FUJITA

The AMS Extension to System Level Design Language—SpecC
IEICE Trans Fundamentals 2006 E89-A: 3397-3407; doi:10.1093/ietfec/e89-a.12.3397 [Abstract] [PDF] [References]  

Kazutoshi WAKABAYASHI

Unified Representation for Speculative Scheduling: Generalized Condition Vector
IEICE Trans Fundamentals 2006 E89-A: 3408-3415; doi:10.1093/ietfec/e89-a.12.3408 [Abstract] [PDF] [References]  

Mitsuru TOMONO, Masaki NAKANISHI, Shigeru YAMASHITA, Kazuo NAKAJIMA, and Katsumasa WATANABE

An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs
IEICE Trans Fundamentals 2006 E89-A: 3416-3426; doi:10.1093/ietfec/e89-a.12.3416 [Abstract] [PDF] [References]  

Nobuhiro DOI, Takashi HORIYAMA, Masaki NAKANISHI, and Shinji KIMURA

Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique
IEICE Trans Fundamentals 2006 E89-A: 3427-3434; doi:10.1093/ietfec/e89-a.12.3427 [Abstract] [PDF] [References]  

Bakhtiar Affendi ROSDI and Atsushi TAKAHASHI

Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits
IEICE Trans Fundamentals 2006 E89-A: 3435-3442; doi:10.1093/ietfec/e89-a.12.3435 [Abstract] [PDF] [References]  

Special Section on VLSI Design and CAD Algorithms -- Papers -- Logic Synthesis

Debatosh DEBNATH and Tsutomu SASAO

Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries
IEICE Trans Fundamentals 2006 E89-A: 3443-3450; doi:10.1093/ietfec/e89-a.12.3443 [Abstract] [PDF] [References]  

Special Section on VLSI Design and CAD Algorithms -- Papers -- Simulation and Verification

Xingwen XU, Shinji KIMURA, Kazunari HORIKAWA, and Takehiko TSUCHIYA

Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification
IEICE Trans Fundamentals 2006 E89-A: 3451-3457; doi:10.1093/ietfec/e89-a.12.3451 [Abstract] [PDF] [References]  

Yuichi NAKAMURA and Takeshi YOSHIMURA

Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs
IEICE Trans Fundamentals 2006 E89-A: 3458-3463; doi:10.1093/ietfec/e89-a.12.3458 [Abstract] [PDF] [References]  

Yuichi NAKAMURA and Kouhei HOSOKAWA

Fast FPGA-Emulation-Based Simulation Environment for Custom Processors
IEICE Trans Fundamentals 2006 E89-A: 3464-3470; doi:10.1093/ietfec/e89-a.12.3464 [Abstract] [PDF] [References]  

Hiroki NAKAHARA, Tsutomu SASAO, and Munehiro MATSUURA

A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator
IEICE Trans Fundamentals 2006 E89-A: 3471-3481; doi:10.1093/ietfec/e89-a.12.3471 [Abstract] [PDF] [References]  

Naoaki OHKUBO and Kimiyoshi USAMI

Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits
IEICE Trans Fundamentals 2006 E89-A: 3482-3490; doi:10.1093/ietfec/e89-a.12.3482 [Abstract] [PDF] [References]  

Takashi SATO, Junji ICHIMIYA, Nobuto ONO, and Masanori HASHIMOTO

On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature
IEICE Trans Fundamentals 2006 E89-A: 3491-3499; doi:10.1093/ietfec/e89-a.12.3491 [Abstract] [PDF] [References]  

Special Section on VLSI Design and CAD Algorithms -- Papers -- Circuit Synthesis

Naofumi HOMMA, Yuki WATANABE, Takafumi AOKI, and Tatsuo HIGUCHI

Formal Design of Arithmetic Circuits Based on Arithmetic Description Language
IEICE Trans Fundamentals 2006 E89-A: 3500-3509; doi:10.1093/ietfec/e89-a.12.3500 [Abstract] [PDF] [References]  

Shinobu NAGAYAMA, Tsutomu SASAO, and Jon T. BUTLER

Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method
IEICE Trans Fundamentals 2006 E89-A: 3510-3518; doi:10.1093/ietfec/e89-a.12.3510 [Abstract] [PDF] [References]  

Kouichi WATANABE, Masashi IMAI, Masaaki KONDO, Hiroshi NAKAMURA, and Takashi NANYA

Design Method of High Performance and Low Power Functional Units Considering Delay Variations
IEICE Trans Fundamentals 2006 E89-A: 3519-3528; doi:10.1093/ietfec/e89-a.12.3519 [Abstract] [PDF] [References]  

Hiroaki YOSHIDA, Makoto IKEDA, and Kunihiro ASADA

A Structural Approach for Transistor Circuit Synthesis
IEICE Trans Fundamentals 2006 E89-A: 3529-3537; doi:10.1093/ietfec/e89-a.12.3529 [Abstract] [PDF] [References]  

Shingo TAKAHASHI, Shuji TSUKIYAMA, Masanori HASHIMOTO, and Isao SHIRAKAWA

A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays
IEICE Trans Fundamentals 2006 E89-A: 3538-3545; doi:10.1093/ietfec/e89-a.12.3538 [Abstract] [PDF] [References]  

Special Section on VLSI Design and CAD Algorithms -- Papers -- Physical Design

Taisuke KAZAMA, Makoto IKEDA, and Kunihiro ASADA

LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil
IEICE Trans Fundamentals 2006 E89-A: 3546-3550; doi:10.1093/ietfec/e89-a.12.3546 [Abstract] [PDF] [References]  

Yoichi TOMIOKA and Atsushi TAKAHASHI

Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages
IEICE Trans Fundamentals 2006 E89-A: 3551-3559; doi:10.1093/ietfec/e89-a.12.3551 [Abstract] [PDF] [References]  

Special Section on VLSI Design and CAD Algorithms -- Papers -- Interconnect

Toshiki KANAMOTO, Tatsuhiko IKEDA, Akira TSUCHIYA, Hidetoshi ONODERA, and Masanori HASHIMOTO

Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design
IEICE Trans Fundamentals 2006 E89-A: 3560-3568; doi:10.1093/ietfec/e89-a.12.3560 [Abstract] [PDF] [References]  

Danardono Dwi ANTONO, Kenichi INAGAKI, Hiroshi KAWAGUCHI, and Takayasu SAKURAI

Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's
IEICE Trans Fundamentals 2006 E89-A: 3569-3578; doi:10.1093/ietfec/e89-a.12.3569 [Abstract] [PDF] [References]  

Takumi UEZONO, Kenichi OKADA, and Kazuya MASU

Statistical Modeling of a Via Distribution for Yield Estimation
IEICE Trans Fundamentals 2006 E89-A: 3579-3584; doi:10.1093/ietfec/e89-a.12.3579 [Abstract] [PDF] [References]  

Akira TSUCHIYA, Masanori HASHIMOTO, and Hidetoshi ONODERA

Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line
IEICE Trans Fundamentals 2006 E89-A: 3585-3593; doi:10.1093/ietfec/e89-a.12.3585 [Abstract] [PDF] [References]  

Special Section on VLSI Design and CAD Algorithms -- Papers -- VLSI Architecture

Yang SONG, Zhenyu LIU, Takeshi IKENAGA, and Satoshi GOTO

A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization
IEICE Trans Fundamentals 2006 E89-A: 3594-3601; doi:10.1093/ietfec/e89-a.12.3594 [Abstract] [PDF] [References]  

Kazunori SHIMIZU, Tatsuyuki ISHIKAWA, Nozomu TOGAWA, Takeshi IKENAGA, and Satoshi GOTO

Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule
IEICE Trans Fundamentals 2006 E89-A: 3602-3612; doi:10.1093/ietfec/e89-a.12.3602 [Abstract] [PDF] [References]  

Win-Bin HUANG, Alvin W. Y. SU, and Yau-Hwang KUO

VLSI Implementation of a Modified Efficient SPIHT Encoder
IEICE Trans Fundamentals 2006 E89-A: 3613-3622; doi:10.1093/ietfec/e89-a.12.3613 [Abstract] [PDF] [References]  

Junichi MIYAKOSHI, Yuichiro MURACHI, Tetsuro MATSUNO, Masaki HAMAMOTO, Takahiro IINUMA, Tomokazu ISHIHARA, Hiroshi KAWAGUCHI, Masayuki MIYAMA, and Masahiko YOSHIMOTO

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture
IEICE Trans Fundamentals 2006 E89-A: 3623-3633; doi:10.1093/ietfec/e89-a.12.3623 [Abstract] [PDF] [References]  

Yasuhiro MORITA, Hidehiro FUJIWARA, Hiroki NOGUCHI, Kentaro KAWAKAMI, Junichi MIYAKOSHI, Shinji MIKAMI, Koji NII, Hiroshi KAWAGUCHI, and Masahiko YOSHIMOTO

A 0.3-V Operating, V_th-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond
IEICE Trans Fundamentals 2006 E89-A: 3634-3641; doi:10.1093/ietfec/e89-a.12.3634 [Abstract] [PDF] [References]  

Kentaro KAWAKAMI, Jun TAKEMURA, Mitsuhiko KURODA, Hiroshi KAWAGUCHI, and Masahiko YOSHIMOTO

A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline
IEICE Trans Fundamentals 2006 E89-A: 3642-3651; doi:10.1093/ietfec/e89-a.12.3642 [Abstract] [PDF] [References]  

Kentaro NAKAHARA, Shin'ichi KOUYAMA, Tomonori IZUMI, Hiroyuki OCHI, and Yukihiro NAKAMURA

Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback
IEICE Trans Fundamentals 2006 E89-A: 3652-3658; doi:10.1093/ietfec/e89-a.12.3652 [Abstract] [PDF] [References]  

Lan-Rong DUNG and Hsueh-Chih YANG

A Parallel-In Folding Technique for High-Order FIR Filter Implementation
IEICE Trans Fundamentals 2006 E89-A: 3659-3665; doi:10.1093/ietfec/e89-a.12.3659 [Abstract] [PDF] [References]  

Special Section on VLSI Design and CAD Algorithms -- Letter -- Interconnect

Toshiki KANAMOTO, Shigekiyo AKUTSU, Tamiyo NAKABAYASHI, Takahiro ICHINOMIYA, Koutaro HACHIYA, Atsushi KUROKAWA, Hiroshi ISHIKAWA, Sakae MUROMOTO, Hiroyuki KOBAYASHI, and Masanori HASHIMOTO

Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation
IEICE Trans Fundamentals 2006 E89-A: 3666-3670; doi:10.1093/ietfec/e89-a.12.3666 [Abstract] [PDF] [References]  

Regular Section -- Papers -- Engineering Acoustics

Yuan WEN, Jun YANG, and Woon-Seng GAN

Target-Oriented Acoustic Radiation Generation Technique for Sound Field Control
IEICE Trans Fundamentals 2006 E89-A: 3671-3677; doi:10.1093/ietfec/e89-a.12.3671 [Abstract] [PDF] [References]  

Regular Section -- Papers -- Digital Signal Processing

Tomoko YOKOKAWA, Masaru KAMADA, Yasuhiro OHTAKI, and Tatsuhiro YONEKURA

Estimation of Color Images by Box Splines from Their Observation through Honeycomb Color Filter
IEICE Trans Fundamentals 2006 E89-A: 3678-3684; doi:10.1093/ietfec/e89-a.12.3678 [Abstract] [PDF] [References]  

Regular Section -- Papers -- Analog Signal Processing

Masahiro YOSHIOKA and Nobuo FUJII

Miller Capacitor with Wide Input Range and Its Application to PLL Loop Filter
IEICE Trans Fundamentals 2006 E89-A: 3685-3692; doi:10.1093/ietfec/e89-a.12.3685 [Abstract] [PDF] [References]  

Regular Section -- Papers -- Nonlinear Problems

Tetsuo NISHI, Norikazu TAKAHASHI, and Hajime HARA

Necessary and Sufficient Conditions for One-Dimensional Discrete-Time Autonomous Binary Cellular Neural Networks to Be Stable
IEICE Trans Fundamentals 2006 E89-A: 3693-3698; doi:10.1093/ietfec/e89-a.12.3693 [Abstract] [PDF] [References]  

Regular Section -- Papers -- Algorithms and Data Structures

Katsuyuki HAGIWARA and Hiroshi ISHITANI

On the Expected Prediction Error of Orthogonal Regression with Variable Components
IEICE Trans Fundamentals 2006 E89-A: 3699-3709; doi:10.1093/ietfec/e89-a.12.3699 [Abstract] [PDF] [References]  

Regular Section -- Papers -- Information Theory

Takashi ISHIDA, Masayuki GOTO, Toshiyasu MATSUSHIMA, and Shigeichi HIRASAWA

Properties of a Word-Valued Source with a Non-prefix-free Word Set
IEICE Trans Fundamentals 2006 E89-A: 3710-3723; doi:10.1093/ietfec/e89-a.12.3710 [Abstract] [PDF] [References]  

Regular Section -- Letters -- Digital Signal Processing

Shin'ichi SHIRAISHI, Miki HASEYAMA, and Hideo KITAJIMA

Steady-State Properties of a CORDIC-Based Adaptive ARMA Lattice Filter
IEICE Trans Fundamentals 2006 E89-A: 3724-3729; doi:10.1093/ietfec/e89-a.12.3724 [Abstract] [PDF] [References]  

Regular Section -- Letters -- Circuit Theory

Hua-Pin CHEN and Kuo-Hsiung WU

Grounded-Capacitor First-Order Filter Using Minimum Components
IEICE Trans Fundamentals 2006 E89-A: 3730-3731; doi:10.1093/ietfec/e89-a.12.3730 [Abstract] [PDF] [References]  

Regular Section -- Letters -- Information Security

InKoo KANG, Kishore SINHA, and Heung-Kyu LEE

New Digital Fingerprint Code Construction Scheme Using Group-Divisible Design
IEICE Trans Fundamentals 2006 E89-A: 3732-3735; doi:10.1093/ietfec/e89-a.12.3732 [Abstract] [PDF] [References]  

Regular Section -- Letters -- Concurrent Systems

Jung-Wook PARK, Byoung-Kon CHOI, and Kyung-Bin SONG

First Derivatives Estimation of Nonlinear Parameters in Hybrid System
IEICE Trans Fundamentals 2006 E89-A: 3736-3738; doi:10.1093/ietfec/e89-a.12.3736 [Abstract] [PDF] [References]  

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