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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 2008 E91-A(4):1062-1070; doi:10.1093/ietfec/e91-a.4.1062
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Copyright © 2008 The Institute of Electronics, Information and Communication Engineers

Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa -- Papers

A Novel Expression of Spatial Correlation by a Random Curved Surface Model and Its Application to LSI Design

Shin-ichi OHKAWA1,2, Hiroo MASUDA1 and Yasuaki INOUE2

1 The authors are with Renesas Technology Corp., Kodaira-shi, 187-8588 Japan. E-mail: okawa.shinichi{at}renesas.com, 2 The authors are with the Graduate School of Information, Production and Systems, Waseda University, Kitakyushu-shi, 808-0135 Japan.

We have proposed a random curved surface model as a new mathematical concept which enables the expression of spatial correlation. The model gives us an appropriate methodology to deal with the systematic components of device variation in an LSI chip. The key idea of the model is the fitting of a polynomial to an array of Gaussian random numbers. The curved surface is expressed by a new extension from the Legendre polynomials to form two-dimensional formulas. The formulas were proven to be suitable to express the spatial correlation with reasonable computational complexity. In this paper, we show that this approach is useful in analyzing characteristics of device variation of actual chips by using experimental data.

Key Words: LSI design, device variation, random curved surface, Gaussian, systematic part

Manuscript received June 26, 2007. Manuscript revised October 2, 2007.

Reference

[1] S. Ohkawa, M. Aoki, and H. Masuda, "A novel expression of spatial correlation with random curved surface," IEICE Technical Report, ICD2006-159, Dec. 2006.

[2] A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K. Gala, and R. Panda, "Statistical delay computation considering spatial correlations," Proc. ASP-DAC, 2003, pp.271–276, Jan. 2003.

[3] S. Ohkawa, M. Aoki, and H. Masuda, "Analysis and characterization of device variation in an LSI chip using an integrated device matrix array," IEEE Trans. Semicond. Manuf., vol.17, no.2, pp.155–165, May 2004.

[4] M. Aoki, S. Ohkawa, and H. Masuda., "Design guidelines and process quality improvement for treatment of device variations in an LSI chip," IEICE Trans. Electron., vol.E88-C, no.5, pp.788–795, May 2005.


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This Article
Right arrow Abstract Freely available
Right arrow Full Text (PDF)
Right arrow Alert me when this article is cited
Right arrow Alert me if a correction is posted
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Right arrow Email this article to a friend
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Right arrow Add to My Personal Archive
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Google Scholar
Right arrow Articles by OHKAWA, S.-i.
Right arrow Articles by INOUE, Y.
Right arrow Search for Related Content
Social Bookmarking
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What's this?