IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 2008 E91-A(2):497-503; doi:10.1093/ietfec/e91-a.2.497

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Copyright © 2008 The Institute of Electronics, Information and Communication Engineers

Special Section on Analog Circuit Techniques and Related Topics -- Papers

A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology

Ching-Yuan YANG¹, Chih-Hsiang CHANG² and Wen-Ger WONG³

¹ The author is with the Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan, R.O.C. E-mail: ycy{at}dragon.nchu.edu.tw, ² The author is with the Graduate Institute of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan, R.O.C., ³ The author is with the Sonix Technology Corp., Hsinchu, Taiwan, R.O.C.

A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N–1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the overall fractional division. The dual-modulus divider introduces a delay-locked-loop network to achieve phase compensation. Operating at the frequency of 3.2 GHz, the measured peak power reduction is around 16 dB for a deviation of 0.37% and a frequency modulation of 33 kHz. The circuit occupies 1.4 x 1.4 mm² in a 0.18-µm CMOS process and consumes 52 mW.

Key Words: spread spectrum clock generation, fractional phase-locked loop, delay-locked loop, phase compensation, fractional divider

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Manuscript received June 14, 2007. Manuscript revised September 2, 2007.

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