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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 2008 E91-A(2):469-475; doi:10.1093/ietfec/e91-a.2.469
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Copyright © 2008 The Institute of Electronics, Information and Communication Engineers

Special Section on Analog Circuit Techniques and Related Topics -- Papers

A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing

Masaya MIYAHARA1 and Akira MATSUZAWA1

1 The authors are with the Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, 152-8552 Japan. E-mail: masaya{at}ssc.pe.titech.ac.jp

This paper proposes a performance model for design of pipelined analog-to-digital converters (ADCs). This model includes the effect of overdrive voltage on the transistor, slewing of the operational amplifier, multi-bit structure of multiplying digital to analog converter (MDAC) and technology scaling. The conversion frequency of ADC is improved by choosing the optimum overdrive voltage of the transistor, an important consideration at smaller design rules. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. The performance model of pipelined ADC shown in this paper is attractive for the optimization of the ADC's performances.

Key Words: analog to digital converter, pipeline operation, switched capacitor amplifier, low voltage operation, overdrive voltage


Manuscript received July 2, 2007. Manuscript revised September 10, 2007.

Reference

[1] S.H. Lewis, H.S. Fetterman, G.F. Gross, Jr., R. Ramachandran, and T.R. Viswanathan, "A 10-b, 20-Msample/s analog-to-digital converter," IEEE J. Solid-State Circuits, vol.27, no.3, pp.351–358, March 1992.

[2] A. Matsuzawa, "Design challenges of analog-to-digital converters in nanoscale CMOS," IEICE Trans. Electron., vol.E90-C, no.4, pp.779–785, April 2007.

[3] M. Yoshioka, M. Kudo, T. Mori, and S. Tsukamoto, "A 0.8 V 10 b 80 MS/s 6.5 mW pipelined ADC with regulated overdrive voltage biasing," IEEE ISSCC 2007, Dig. of Tech. Papers, pp.452–453, Feb. 2007.

[4] M. Miyahara and A. Matsuzawa, "The effects of switch resistances on pipelined ADC performances and the optimization for the settling time," IEICE Trans. Electron., vol.E90-C, no.6, pp.1165–1171, June 2007.

[5] S.-Y. Chuang and T.L. Sculley, "A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter," IEEE J. Solid-State Circuits, vol.37, no.6, pp.674–683, June 2002.

[6] C.C. Enz, F. Krummenacher, and E. Vittoz, "An analytical MOS transistor model valid in all resions of operation and dedicated to low-voltage and low-current applications," Analog Integr. Circuits Signal Process., vol.8, pp.83–114, 1995.


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This Article
Right arrow Abstract Freely available
Right arrow Full Text (PDF)
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Right arrow Articles by MIYAHARA, M.
Right arrow Articles by MATSUZAWA, A.
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 Add to CiteULike   Add to Connotea   Add to Del.icio.us  
What's this?