Copyright © 2008 The Institute of Electronics, Information and Communication Engineers
Special Section on Analog Circuit Techniques and Related Topics -- Papers |
Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture
1 The authors are with the Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan. E-mail: petero{at}spic.ee.ncku.edu.tw
This paper proposes useful circuit structures for achieving a low-voltage/low-power pipelined ADC based on switched-opamp architecture. First, a novel unity-feedback-factor sample-and-hold which manipulates the features of switched-opamp technique is presented. Second, opamp-sharing is merged into switched-opamp structure with a proposed dual-output opamp configuration. A 0.8-V, 9-bit, 10-Msample/s pipelined ADC is designed to verify the proposed circuit. Simulation results using a 0.18-µm CMOS 1P6M process demonstrate the figure-of-merit of this pipelined ADC is only 0.71 pJ/step.
Key Words: low-voltage, switched-opamp, sample-and-hold, opamp-sharing, pipelined ADC
Manuscript received June 21, 2007. Manuscript revised September 10, 2007.
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