Copyright © 2008 The Institute of Electronics, Information and Communication Engineers
Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa -- Papers |
Hardware Neural Network for a Visual Inspection System
1 The authors are with Laboratory for Brainware/Laboratory for Nanoelectronics and Spintronics Research Institute of Electrical Communication, Tohoku University, Sendai-shi, 980-8577 Japan. E-mail: ab1000{at}nakajima.riec.tohoku.ac.jp
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Abstract |
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The visual inspection of defects in products is heavily dependent on human experience and instinct. In this situation, it is difficult to reduce the production costs and to shorten the inspection time and hence the total process time. Consequently people involved in this area desire an automatic inspection system. In this paper, we propose a hardware neural network, which is expected to provide high-speed operation for automatic inspection of products. Since neural networks can learn, this is a suitable method for self-adjustment of criteria for classification. To achieve high-speed operation, we use parallel and pipelining techniques. Furthermore, we use a piecewise linear function instead of a conventional activation function in order to save hardware resources. Consequently, our proposed hardware neural network achieved 6GCPS and 2GCUPS, which in our test sample proved to be sufficiently fast.
Key Words: hardware, visual inspection system, back-propagation, PCI-BUS, FPGA
Manuscript received July 1, 2007. Manuscript revised October 6, 2007.