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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 2008 E91-A(4):1044-1053; doi:10.1093/ietfec/e91-a.4.1044
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Copyright © 2008 The Institute of Electronics, Information and Communication Engineers

Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa -- Papers

Novel Register Sharing in Datapath for Structural Robustness against Delay Variation

Keisuke INOUE1, Mineo KANEKO1 and Tsuyoshi IWAGAKI1

1 The authors are with the School of Information Science, Japan Advanced Institute of Science and Technology, Nomi-shi, 923-1292 Japan. E-mail: k-inoue{at}jaist.ac.jp


  Abstract

As the feature size of VLSI becomes smaller, delay variations become a serious problem in VLSI. In this paper, we propose a novel class of robustness for a datapath against delay variations, which is named structural robustness against delay variation (SRV), and propose sufficient conditions for a datapath to have SRV. A resultant circuit designed under these conditions has a larger timing margin to delay variations than previous designs without sacrificing effective computation time. In addition, under any degree of delay variations, we can always find an available clock frequency for a datapath having SRV property to operate correctly, which could be a preferable characteristic in IP-based design.

Key Words: datapath synthesis, delay variation, register assignment, setup and hold constraints

Manuscript received June 26, 2007.


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