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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 2008 E91-A(2):542-549; doi:10.1093/ietfec/e91-a.2.542
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Copyright © 2008 The Institute of Electronics, Information and Communication Engineers

Special Section on Analog Circuit Techniques and Related Topics -- Papers

A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion*

Bo YANG1, Hiroshi MURATA1 and Shigetoshi NAKATAKE1

1 The authors are with the University of Kitakyushu, Kitakyushu-shi, 808-0135 Japan. E-mail: bo.yang{at}env.kitakyu-u.ac.jp


  Abstract

This paper addresses the on-resistance (Ron) extraction of the DMOS based driver in Power IC designs. The proposed method can extract Ron of a driver from its layout data for the arbitrarily shaped metallization patterns. Such a driver is usually composed of arbitrarily shaped metals, arrayed vias, and DMOS transistors. We use FEM to extract the parasitic resistance of the source/drain metals since its strong contribution to Ron. In order to handle the large design case and accelerate the extraction process, a domain decomposition with virtual terminal insertion method is introduced, which succeeds in extraction for a set of industrial test cases including those the FEM without domain decomposition failed in. For a layout in which the DMOS cells are regularly placed, a sub-domain reuse procedure is also proposed, which obtained a dramatic speedup for the extraction. Even without the sub-domain reuse, our method still shows advantage in runtime and memory usage according to the simulation results.

Key Words: DMOS, finite element method, domain decomposition, sub-domain reuse, resistance extraction

Manuscript received June 26, 2007. Manuscript revised September 14, 2007.

* The abbreviation of this paper has been published in MWSCAS2007.


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