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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 2008 E91-A(2):504-512; doi:10.1093/ietfec/e91-a.2.504
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Copyright © 2008 The Institute of Electronics, Information and Communication Engineers

Special Section on Analog Circuit Techniques and Related Topics -- Papers

A New Low-Power 13.56-MHz CMOS Ring Oscillator with Low Sensitivity of fOSC to VDD

Felix TIMISCHL1, Takahiro INOUE1, Akio TSUNEDA1 and Daisuke MASUNAGA1

1 The authors are with the Department of Computer Science and Electrical Engineering, Graduate School of Science and Technology, Kumamoto University, Kumamoto-shi, 860-8555 Japan. E-mail: timischl{at}st.eecs.kumamoto-u.ac.jp


  Abstract

A design of a low-power CMOS ring oscillator for an application to a 13.56 MHz clock generator in an implantable RFID tag is proposed. The circuit is based on a novel voltage inverter, which is an improved version of the conventional current-source loaded inverter. The proposed circuit enables low-power operation and low sensitivity of the oscillation frequency, fOSC, to decay of the power supply VDD. By employing a gm-boosting subcircuit, power dissipation is decreased to 49 µW at fOSC = 13.56 MHz. The sensitivity of fOSC to VDD is reduced to –0.02 at fOSC = 13.56 MHz thanks to the use of composite high-impedance current sources.

Key Words: CMOS, ring oscillator, low power, gm-booster, VMDD-dependency, composite transistor, figure of merit

Manuscript received June 15, 2007. Manuscript revised September 8, 2007.


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