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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 2008 E91-A(2):469-475; doi:10.1093/ietfec/e91-a.2.469
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Copyright © 2008 The Institute of Electronics, Information and Communication Engineers

Special Section on Analog Circuit Techniques and Related Topics -- Papers

A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing

Masaya MIYAHARA1 and Akira MATSUZAWA1

1 The authors are with the Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, 152-8552 Japan. E-mail: masaya{at}ssc.pe.titech.ac.jp


  Abstract

This paper proposes a performance model for design of pipelined analog-to-digital converters (ADCs). This model includes the effect of overdrive voltage on the transistor, slewing of the operational amplifier, multi-bit structure of multiplying digital to analog converter (MDAC) and technology scaling. The conversion frequency of ADC is improved by choosing the optimum overdrive voltage of the transistor, an important consideration at smaller design rules. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. The performance model of pipelined ADC shown in this paper is attractive for the optimization of the ADC's performances.

Key Words: analog to digital converter, pipeline operation, switched capacitor amplifier, low voltage operation, overdrive voltage

Manuscript received July 2, 2007. Manuscript revised September 10, 2007.


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