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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 2008 E91-A(2):454-460; doi:10.1093/ietfec/e91-a.2.454
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Copyright © 2008 The Institute of Electronics, Information and Communication Engineers

Special Section on Analog Circuit Techniques and Related Topics -- Papers

1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters

Takeshi UENO1, Tomohiko ITO1, Daisuke KUROSE1, Takafumi YAMAJI1 and Tetsuro ITAKURA1

1 The authors are with the Corporate Research & Development Center, Toshiba Corporation, Kawasaki-shi, 212-8582 Japan. E-mail: take.ueno{at}toshiba.co.jp


  Abstract

This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, we employed the I/Q amplifier sharing technique [1] in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are 58.6 dB and 52.2 dB, respectively.

Key Words: pipelined A/D converter, amplifier sharing, common-source, common-mode feedforward

Manuscript received June 11, 2007. Manuscript revised August 22, 2007.


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