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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 2005 E88-A(12):3453-3462; doi:10.1093/ietfec/e88-a.12.3453
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Copyright © 2005 The Institute of Electronics, Information and Communication Engineers

Special Section on VLSI Design and CAD Algorithms -- Papers -- Interconnect

Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance

Atsushi KUROKAWA1, Masanori HASHIMOTO2, Akira KASEBE3, Zhangcai HUANG4, Yun YANG4, Yasuaki INOUE4, Ryosuke INAGAKI1,4 and Hiroo MASUDA1

1 The authors are with STARC, Yokohama-shi, 222-0033 Japan. E-mail: kurokawa{at}starc.or.jp, 2 The author is with Osaka University, Suita-shi, 565-0871 Japan., 3 The author is with Meitec Corp., Tokyo, 104-0061 Japan., 4 The authors are with Waseda University, Kitakyushu-shi, 808-0135 Japan.

Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2–10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

Key Words: capacitance formula, capacitance calculation, capacitance extraction, interconnect capacitance

Manuscript received March 14, 2005. Manuscript revised June 9, 2005. Final manuscript received August 2, 2005.


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